2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
4 * SPDX-License-Identifier: GPL-2.0
11 #include <asm/types.h>
13 #include <asm/arch/powergate.h>
14 #include <asm/arch/tegra.h>
16 #define PWRGATE_TOGGLE 0x30
17 #define PWRGATE_TOGGLE_START (1 << 8)
19 #define REMOVE_CLAMPING 0x34
21 #define PWRGATE_STATUS 0x38
23 static int tegra_powergate_set(enum tegra_powergate id, bool state)
25 u32 value, mask = state ? (1 << id) : 0, old_mask;
26 unsigned long start, timeout = 25;
28 value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
29 old_mask = value & (1 << id);
34 writel(PWRGATE_TOGGLE_START | id, NV_PA_PMC_BASE + PWRGATE_TOGGLE);
38 while (get_timer(start) < timeout) {
39 value = readl(NV_PA_PMC_BASE + PWRGATE_STATUS);
40 if ((value & (1 << id)) == mask)
47 int tegra_powergate_power_on(enum tegra_powergate id)
49 return tegra_powergate_set(id, true);
52 int tegra_powergate_power_off(enum tegra_powergate id)
54 return tegra_powergate_set(id, false);
57 static int tegra_powergate_remove_clamping(enum tegra_powergate id)
62 * The REMOVE_CLAMPING register has the bits for the PCIE and VDEC
63 * partitions reversed. This was originally introduced on Tegra20 but
64 * has since been carried forward for backwards-compatibility.
66 if (id == TEGRA_POWERGATE_VDEC)
67 value = 1 << TEGRA_POWERGATE_PCIE;
68 else if (id == TEGRA_POWERGATE_PCIE)
69 value = 1 << TEGRA_POWERGATE_VDEC;
73 writel(value, NV_PA_PMC_BASE + REMOVE_CLAMPING);
78 int tegra_powergate_sequence_power_up(enum tegra_powergate id,
79 enum periph_id periph)
83 reset_set_enable(periph, 1);
85 err = tegra_powergate_power_on(id);
93 err = tegra_powergate_remove_clamping(id);
99 reset_set_enable(periph, 0);