1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
8 #include <linux/arm-smccc.h>
11 #include <asm/arch-tegra/pmc.h>
13 DECLARE_GLOBAL_DATA_PTR;
15 #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
16 static bool tegra_pmc_detect_tz_only(void)
18 static bool initialized = false;
19 static bool is_tz_only = false;
23 saved = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
24 value = saved ^ 0xffffffff;
26 if (value == 0xffffffff)
29 /* write pattern and read it back */
30 writel(value, NV_PA_PMC_BASE + PMC_SCRATCH0);
31 value = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
33 /* if we read all-zeroes, access is restricted to TZ only */
35 debug("access to PMC is restricted to TZ\n");
38 /* restore original value */
39 writel(saved, NV_PA_PMC_BASE + PMC_SCRATCH0);
49 uint32_t tegra_pmc_readl(unsigned long offset)
51 #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
52 if (tegra_pmc_detect_tz_only()) {
53 struct arm_smccc_res res;
55 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
58 printf("%s(): SMC failed: %lu\n", __func__, res.a0);
64 return readl(NV_PA_PMC_BASE + offset);
67 void tegra_pmc_writel(u32 value, unsigned long offset)
69 #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
70 if (tegra_pmc_detect_tz_only()) {
71 struct arm_smccc_res res;
73 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
74 value, 0, 0, 0, 0, &res);
76 printf("%s(): SMC failed: %lu\n", __func__, res.a0);
82 writel(value, NV_PA_PMC_BASE + offset);
85 void reset_cpu(ulong addr)
89 value = tegra_pmc_readl(PMC_CNTRL);
90 value |= PMC_CNTRL_MAIN_RST;
91 tegra_pmc_writel(value, PMC_CNTRL);