1 /* SPDX-License-Identifier: GPL-2.0 */
3 * Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved.
9 #include <linux/arm-smccc.h>
12 #include <asm/arch-tegra/pmc.h>
14 DECLARE_GLOBAL_DATA_PTR;
16 #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
17 static bool tegra_pmc_detect_tz_only(void)
19 static bool initialized = false;
20 static bool is_tz_only = false;
24 saved = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
25 value = saved ^ 0xffffffff;
27 if (value == 0xffffffff)
30 /* write pattern and read it back */
31 writel(value, NV_PA_PMC_BASE + PMC_SCRATCH0);
32 value = readl(NV_PA_PMC_BASE + PMC_SCRATCH0);
34 /* if we read all-zeroes, access is restricted to TZ only */
36 debug("access to PMC is restricted to TZ\n");
39 /* restore original value */
40 writel(saved, NV_PA_PMC_BASE + PMC_SCRATCH0);
50 uint32_t tegra_pmc_readl(unsigned long offset)
52 #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
53 if (tegra_pmc_detect_tz_only()) {
54 struct arm_smccc_res res;
56 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_READ, offset, 0, 0,
59 printf("%s(): SMC failed: %lu\n", __func__, res.a0);
65 return readl(NV_PA_PMC_BASE + offset);
68 void tegra_pmc_writel(u32 value, unsigned long offset)
70 #if IS_ENABLED(CONFIG_TEGRA_PMC_SECURE)
71 if (tegra_pmc_detect_tz_only()) {
72 struct arm_smccc_res res;
74 arm_smccc_smc(TEGRA_SMC_PMC, TEGRA_SMC_PMC_WRITE, offset,
75 value, 0, 0, 0, 0, &res);
77 printf("%s(): SMC failed: %lu\n", __func__, res.a0);
83 writel(value, NV_PA_PMC_BASE + offset);
86 void reset_cpu(ulong addr)
90 value = tegra_pmc_readl(PMC_CNTRL);
91 value |= PMC_CNTRL_MAIN_RST;
92 tegra_pmc_writel(value, PMC_CNTRL);