1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
4 * Copyright (c) 2011 The Chromium OS Authors.
9 #include <asm/arch/pinmux.h>
11 /* return 1 if a pingrp is in range */
12 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
14 /* return 1 if a pmux_func is in range */
15 #define pmux_func_isvalid(func) \
16 (((func) >= 0) && ((func) < PMUX_FUNC_COUNT))
18 /* return 1 if a pin_pupd_is in range */
19 #define pmux_pin_pupd_isvalid(pupd) \
20 (((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP))
22 /* return 1 if a pin_tristate_is in range */
23 #define pmux_pin_tristate_isvalid(tristate) \
24 (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
26 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
27 /* return 1 if a pin_io_is in range */
28 #define pmux_pin_io_isvalid(io) \
29 (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
32 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
33 /* return 1 if a pin_lock is in range */
34 #define pmux_pin_lock_isvalid(lock) \
35 (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
38 #ifdef TEGRA_PMX_PINS_HAVE_OD
39 /* return 1 if a pin_od is in range */
40 #define pmux_pin_od_isvalid(od) \
41 (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
44 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
45 /* return 1 if a pin_ioreset_is in range */
46 #define pmux_pin_ioreset_isvalid(ioreset) \
47 (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
48 ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
51 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
52 /* return 1 if a pin_rcv_sel_is in range */
53 #define pmux_pin_rcv_sel_isvalid(rcv_sel) \
54 (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
55 ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
58 #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
59 /* return 1 if a pin_e_io_hv is in range */
60 #define pmux_pin_e_io_hv_isvalid(e_io_hv) \
61 (((e_io_hv) >= PMUX_PIN_E_IO_HV_NORMAL) && \
62 ((e_io_hv) <= PMUX_PIN_E_IO_HV_HIGH))
65 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
66 #define pmux_lpmd_isvalid(lpm) \
67 (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
70 #if defined(TEGRA_PMX_PINS_HAVE_SCHMT) || defined(TEGRA_PMX_GRPS_HAVE_SCHMT)
71 #define pmux_schmt_isvalid(schmt) \
72 (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
75 #if defined(TEGRA_PMX_PINS_HAVE_HSM) || defined(TEGRA_PMX_GRPS_HAVE_HSM)
76 #define pmux_hsm_isvalid(hsm) \
77 (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
80 #define _R(offset) (u32 *)((unsigned long)NV_PA_APB_MISC_BASE + (offset))
82 #if defined(CONFIG_TEGRA20)
84 #define MUX_REG(grp) _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4))
85 #define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2)
87 #define PULL_REG(grp) _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4))
88 #define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2)
90 #define TRI_REG(grp) _R(0x14 + (((grp) / 32) * 4))
91 #define TRI_SHIFT(grp) ((grp) % 32)
95 #define REG(pin) _R(0x3000 + ((pin) * 4))
97 #define MUX_REG(pin) REG(pin)
98 #define MUX_SHIFT(pin) 0
100 #define PULL_REG(pin) REG(pin)
101 #define PULL_SHIFT(pin) 2
103 #define TRI_REG(pin) REG(pin)
104 #define TRI_SHIFT(pin) 4
106 #endif /* CONFIG_TEGRA20 */
108 #define DRV_REG(group) _R(TEGRA_PMX_SOC_DRV_GROUP_BASE_REG + ((group) * 4))
110 #define MIPIPADCTRL_REG(group) _R(TEGRA_PMX_SOC_MIPIPADCTRL_BASE_REG + ((group) * 4))
113 * We could force arch-tegraNN/pinmux.h to define all of these. However,
114 * that's a lot of defines, and for now it's manageable to just put a
115 * special case here. It's possible this decision will change with future
118 #ifdef CONFIG_TEGRA210
121 #ifdef TEGRA_PMX_PINS_HAVE_HSM
124 #define E_IO_HV_SHIFT 10
126 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT
127 #define SCHMT_SHIFT 12
133 #define IO_RESET_SHIFT 8
134 #define RCV_SEL_SHIFT 9
137 #ifdef TEGRA_PMX_SOC_HAS_IO_CLAMPING
138 /* This register/field only exists on Tegra114 and later */
139 #define APB_MISC_PP_PINMUX_GLOBAL_0 0x40
140 #define CLAMP_INPUTS_WHEN_TRISTATED 1
142 void pinmux_set_tristate_input_clamping(void)
144 u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
146 setbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
149 void pinmux_clear_tristate_input_clamping(void)
151 u32 *reg = _R(APB_MISC_PP_PINMUX_GLOBAL_0);
153 clrbits_le32(reg, CLAMP_INPUTS_WHEN_TRISTATED);
157 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
159 u32 *reg = MUX_REG(pin);
163 if (func == PMUX_FUNC_DEFAULT)
166 /* Error check on pin and func */
167 assert(pmux_pingrp_isvalid(pin));
168 assert(pmux_func_isvalid(func));
170 if (func >= PMUX_FUNC_RSVD1) {
171 mux = (func - PMUX_FUNC_RSVD1) & 3;
173 /* Search for the appropriate function */
174 for (i = 0; i < 4; i++) {
175 if (tegra_soc_pingroups[pin].funcs[i] == func) {
184 val &= ~(3 << MUX_SHIFT(pin));
185 val |= (mux << MUX_SHIFT(pin));
189 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
191 u32 *reg = PULL_REG(pin);
194 /* Error check on pin and pupd */
195 assert(pmux_pingrp_isvalid(pin));
196 assert(pmux_pin_pupd_isvalid(pupd));
199 val &= ~(3 << PULL_SHIFT(pin));
200 val |= (pupd << PULL_SHIFT(pin));
204 static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
206 u32 *reg = TRI_REG(pin);
209 /* Error check on pin */
210 assert(pmux_pingrp_isvalid(pin));
211 assert(pmux_pin_tristate_isvalid(tri));
214 if (tri == PMUX_TRI_TRISTATE)
215 val |= (1 << TRI_SHIFT(pin));
217 val &= ~(1 << TRI_SHIFT(pin));
221 void pinmux_tristate_enable(enum pmux_pingrp pin)
223 pinmux_set_tristate(pin, PMUX_TRI_TRISTATE);
226 void pinmux_tristate_disable(enum pmux_pingrp pin)
228 pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
231 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
232 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
237 if (io == PMUX_PIN_NONE)
240 /* Error check on pin and io */
241 assert(pmux_pingrp_isvalid(pin));
242 assert(pmux_pin_io_isvalid(io));
245 if (io == PMUX_PIN_INPUT)
246 val |= (io & 1) << IO_SHIFT;
248 val &= ~(1 << IO_SHIFT);
253 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
254 static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
259 if (lock == PMUX_PIN_LOCK_DEFAULT)
262 /* Error check on pin and lock */
263 assert(pmux_pingrp_isvalid(pin));
264 assert(pmux_pin_lock_isvalid(lock));
267 if (lock == PMUX_PIN_LOCK_ENABLE) {
268 val |= (1 << LOCK_SHIFT);
270 if (val & (1 << LOCK_SHIFT))
271 printf("%s: Cannot clear LOCK bit!\n", __func__);
272 val &= ~(1 << LOCK_SHIFT);
280 #ifdef TEGRA_PMX_PINS_HAVE_OD
281 static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
286 if (od == PMUX_PIN_OD_DEFAULT)
289 /* Error check on pin and od */
290 assert(pmux_pingrp_isvalid(pin));
291 assert(pmux_pin_od_isvalid(od));
294 if (od == PMUX_PIN_OD_ENABLE)
295 val |= (1 << OD_SHIFT);
297 val &= ~(1 << OD_SHIFT);
304 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
305 static void pinmux_set_ioreset(enum pmux_pingrp pin,
306 enum pmux_pin_ioreset ioreset)
311 if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
314 /* Error check on pin and ioreset */
315 assert(pmux_pingrp_isvalid(pin));
316 assert(pmux_pin_ioreset_isvalid(ioreset));
319 if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
320 val |= (1 << IO_RESET_SHIFT);
322 val &= ~(1 << IO_RESET_SHIFT);
329 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
330 static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
331 enum pmux_pin_rcv_sel rcv_sel)
336 if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
339 /* Error check on pin and rcv_sel */
340 assert(pmux_pingrp_isvalid(pin));
341 assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
344 if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
345 val |= (1 << RCV_SEL_SHIFT);
347 val &= ~(1 << RCV_SEL_SHIFT);
354 #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
355 static void pinmux_set_e_io_hv(enum pmux_pingrp pin,
356 enum pmux_pin_e_io_hv e_io_hv)
361 if (e_io_hv == PMUX_PIN_E_IO_HV_DEFAULT)
364 /* Error check on pin and e_io_hv */
365 assert(pmux_pingrp_isvalid(pin));
366 assert(pmux_pin_e_io_hv_isvalid(e_io_hv));
369 if (e_io_hv == PMUX_PIN_E_IO_HV_HIGH)
370 val |= (1 << E_IO_HV_SHIFT);
372 val &= ~(1 << E_IO_HV_SHIFT);
379 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT
380 static void pinmux_set_schmt(enum pmux_pingrp pin, enum pmux_schmt schmt)
385 /* NONE means unspecified/do not change/use POR value */
386 if (schmt == PMUX_SCHMT_NONE)
389 /* Error check pad */
390 assert(pmux_pingrp_isvalid(pin));
391 assert(pmux_schmt_isvalid(schmt));
394 if (schmt == PMUX_SCHMT_ENABLE)
395 val |= (1 << SCHMT_SHIFT);
397 val &= ~(1 << SCHMT_SHIFT);
404 #ifdef TEGRA_PMX_PINS_HAVE_HSM
405 static void pinmux_set_hsm(enum pmux_pingrp pin, enum pmux_hsm hsm)
410 /* NONE means unspecified/do not change/use POR value */
411 if (hsm == PMUX_HSM_NONE)
414 /* Error check pad */
415 assert(pmux_pingrp_isvalid(pin));
416 assert(pmux_hsm_isvalid(hsm));
419 if (hsm == PMUX_HSM_ENABLE)
420 val |= (1 << HSM_SHIFT);
422 val &= ~(1 << HSM_SHIFT);
429 static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
431 enum pmux_pingrp pin = config->pingrp;
433 pinmux_set_func(pin, config->func);
434 pinmux_set_pullupdown(pin, config->pull);
435 pinmux_set_tristate(pin, config->tristate);
436 #ifdef TEGRA_PMX_PINS_HAVE_E_INPUT
437 pinmux_set_io(pin, config->io);
439 #ifdef TEGRA_PMX_PINS_HAVE_LOCK
440 pinmux_set_lock(pin, config->lock);
442 #ifdef TEGRA_PMX_PINS_HAVE_OD
443 pinmux_set_od(pin, config->od);
445 #ifdef TEGRA_PMX_PINS_HAVE_IO_RESET
446 pinmux_set_ioreset(pin, config->ioreset);
448 #ifdef TEGRA_PMX_PINS_HAVE_RCV_SEL
449 pinmux_set_rcv_sel(pin, config->rcv_sel);
451 #ifdef TEGRA_PMX_PINS_HAVE_E_IO_HV
452 pinmux_set_e_io_hv(pin, config->e_io_hv);
454 #ifdef TEGRA_PMX_PINS_HAVE_SCHMT
455 pinmux_set_schmt(pin, config->schmt);
457 #ifdef TEGRA_PMX_PINS_HAVE_HSM
458 pinmux_set_hsm(pin, config->hsm);
462 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
467 for (i = 0; i < len; i++)
468 pinmux_config_pingrp(&config[i]);
471 #ifdef TEGRA_PMX_SOC_HAS_DRVGRPS
473 #define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
475 #define pmux_slw_isvalid(slw) \
476 (((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
478 #define pmux_drv_isvalid(drv) \
479 (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
481 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
484 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
485 #define SCHMT_SHIFT 3
487 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
489 #define LPMD_MASK (3 << LPMD_SHIFT)
492 * Note that the following DRV* and SLW* defines are accurate for many drive
493 * groups on many SoCs. We really need a per-group data structure to solve
494 * this, since the fields are in different positions/sizes in different
495 * registers (for different groups).
497 * On Tegra30/114/124, the DRV*_SHIFT values vary.
498 * On Tegra30, the SLW*_SHIFT values vary.
499 * On Tegra30/114/124/210, the DRV*_MASK values vary, although the values
500 * below are wide enough to cover the widest fields, and hopefully don't
501 * interfere with any other fields.
502 * On Tegra30, the SLW*_MASK values vary, but we can't use a value that's
503 * wide enough to cover all cases, since that would cause the field to
504 * overlap with other fields in the narrower cases.
506 #define DRVDN_SHIFT 12
507 #define DRVDN_MASK (0x7F << DRVDN_SHIFT)
508 #define DRVUP_SHIFT 20
509 #define DRVUP_MASK (0x7F << DRVUP_SHIFT)
510 #define SLWR_SHIFT 28
511 #define SLWR_MASK (3 << SLWR_SHIFT)
512 #define SLWF_SHIFT 30
513 #define SLWF_MASK (3 << SLWF_SHIFT)
515 static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
517 u32 *reg = DRV_REG(grp);
520 /* NONE means unspecified/do not change/use POR value */
521 if (slwf == PMUX_SLWF_NONE)
524 /* Error check on pad and slwf */
525 assert(pmux_drvgrp_isvalid(grp));
526 assert(pmux_slw_isvalid(slwf));
530 val |= (slwf << SLWF_SHIFT);
536 static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
538 u32 *reg = DRV_REG(grp);
541 /* NONE means unspecified/do not change/use POR value */
542 if (slwr == PMUX_SLWR_NONE)
545 /* Error check on pad and slwr */
546 assert(pmux_drvgrp_isvalid(grp));
547 assert(pmux_slw_isvalid(slwr));
551 val |= (slwr << SLWR_SHIFT);
557 static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
559 u32 *reg = DRV_REG(grp);
562 /* NONE means unspecified/do not change/use POR value */
563 if (drvup == PMUX_DRVUP_NONE)
566 /* Error check on pad and drvup */
567 assert(pmux_drvgrp_isvalid(grp));
568 assert(pmux_drv_isvalid(drvup));
572 val |= (drvup << DRVUP_SHIFT);
578 static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
580 u32 *reg = DRV_REG(grp);
583 /* NONE means unspecified/do not change/use POR value */
584 if (drvdn == PMUX_DRVDN_NONE)
587 /* Error check on pad and drvdn */
588 assert(pmux_drvgrp_isvalid(grp));
589 assert(pmux_drv_isvalid(drvdn));
593 val |= (drvdn << DRVDN_SHIFT);
599 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
600 static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
602 u32 *reg = DRV_REG(grp);
605 /* NONE means unspecified/do not change/use POR value */
606 if (lpmd == PMUX_LPMD_NONE)
609 /* Error check pad and lpmd value */
610 assert(pmux_drvgrp_isvalid(grp));
611 assert(pmux_lpmd_isvalid(lpmd));
615 val |= (lpmd << LPMD_SHIFT);
622 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
623 static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
625 u32 *reg = DRV_REG(grp);
628 /* NONE means unspecified/do not change/use POR value */
629 if (schmt == PMUX_SCHMT_NONE)
632 /* Error check pad */
633 assert(pmux_drvgrp_isvalid(grp));
634 assert(pmux_schmt_isvalid(schmt));
637 if (schmt == PMUX_SCHMT_ENABLE)
638 val |= (1 << SCHMT_SHIFT);
640 val &= ~(1 << SCHMT_SHIFT);
647 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
648 static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
650 u32 *reg = DRV_REG(grp);
653 /* NONE means unspecified/do not change/use POR value */
654 if (hsm == PMUX_HSM_NONE)
657 /* Error check pad */
658 assert(pmux_drvgrp_isvalid(grp));
659 assert(pmux_hsm_isvalid(hsm));
662 if (hsm == PMUX_HSM_ENABLE)
663 val |= (1 << HSM_SHIFT);
665 val &= ~(1 << HSM_SHIFT);
672 static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
674 enum pmux_drvgrp grp = config->drvgrp;
676 pinmux_set_drvup_slwf(grp, config->slwf);
677 pinmux_set_drvdn_slwr(grp, config->slwr);
678 pinmux_set_drvup(grp, config->drvup);
679 pinmux_set_drvdn(grp, config->drvdn);
680 #ifdef TEGRA_PMX_GRPS_HAVE_LPMD
681 pinmux_set_lpmd(grp, config->lpmd);
683 #ifdef TEGRA_PMX_GRPS_HAVE_SCHMT
684 pinmux_set_schmt(grp, config->schmt);
686 #ifdef TEGRA_PMX_GRPS_HAVE_HSM
687 pinmux_set_hsm(grp, config->hsm);
691 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
696 for (i = 0; i < len; i++)
697 pinmux_config_drvgrp(&config[i]);
699 #endif /* TEGRA_PMX_SOC_HAS_DRVGRPS */
701 #ifdef TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS
703 #define pmux_mipipadctrlgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_MIPIPADCTRLGRP_COUNT))
705 static void pinmux_mipipadctrl_set_func(enum pmux_mipipadctrlgrp grp,
708 u32 *reg = MIPIPADCTRL_REG(grp);
712 if (func == PMUX_FUNC_DEFAULT)
715 /* Error check grp and func */
716 assert(pmux_mipipadctrlgrp_isvalid(grp));
717 assert(pmux_func_isvalid(func));
719 if (func >= PMUX_FUNC_RSVD1) {
720 mux = (func - PMUX_FUNC_RSVD1) & 1;
722 /* Search for the appropriate function */
723 for (i = 0; i < 2; i++) {
724 if (tegra_soc_mipipadctrl_groups[grp].funcs[i]
739 static void pinmux_config_mipipadctrlgrp(const struct pmux_mipipadctrlgrp_config *config)
741 enum pmux_mipipadctrlgrp grp = config->grp;
743 pinmux_mipipadctrl_set_func(grp, config->func);
746 void pinmux_config_mipipadctrlgrp_table(
747 const struct pmux_mipipadctrlgrp_config *config, int len)
751 for (i = 0; i < len; i++)
752 pinmux_config_mipipadctrlgrp(&config[i]);
754 #endif /* TEGRA_PMX_SOC_HAS_MIPI_PAD_CTRL_GRPS */