1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved.
9 #include <asm/arch/clock.h>
10 #include <asm/arch/gp_padctrl.h>
11 #include <asm/arch/pinmux.h>
12 #include <asm/arch/tegra.h>
13 #include <asm/arch-tegra/clk_rst.h>
14 #include <asm/arch-tegra/pmc.h>
15 #include <asm/arch-tegra/scu.h>
16 #include <linux/delay.h>
19 int get_num_cpus(void)
21 struct apb_misc_gp_ctlr *gp;
23 debug("%s entry\n", __func__);
25 gp = (struct apb_misc_gp_ctlr *)NV_PA_APB_MISC_GP_BASE;
26 rev = (readl(&gp->hidrev) & HIDREV_CHIPID_MASK) >> HIDREV_CHIPID_SHIFT;
43 * Timing tables for each SOC for all four oscillator options.
45 struct clk_pll_table tegra_pll_x_table[TEGRA_SOC_CNT][CLOCK_OSC_FREQ_COUNT] = {
49 * Register Field Bits Width
50 * ------------------------------
52 * PLLX_BASE n 17: 8 10
54 * PLLX_MISC cpcon 11: 8 4
57 { .n = 1000, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
58 { .n = 625, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
59 { .n = 1000, .m = 12, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
60 { .n = 1000, .m = 26, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
61 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
62 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
67 * Register Field Bits Width
68 * ------------------------------
70 * PLLX_BASE n 17: 8 10
72 * PLLX_MISC cpcon 11: 8 4
75 { .n = 923, .m = 10, .p = 0, .cpcon = 12 }, /* OSC: 13.0 MHz */
76 { .n = 750, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
77 { .n = 600, .m = 6, .p = 0, .cpcon = 12 }, /* OSC: 12.0 MHz */
78 { .n = 600, .m = 13, .p = 0, .cpcon = 12 }, /* OSC: 26.0 MHz */
79 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
80 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
85 * Register Field Bits Width
86 * ------------------------------
88 * PLLX_BASE n 17: 8 10
90 * PLLX_MISC cpcon 11: 8 4
93 { .n = 600, .m = 13, .p = 0, .cpcon = 8 }, /* OSC: 13.0 MHz */
94 { .n = 500, .m = 16, .p = 0, .cpcon = 8 }, /* OSC: 19.2 MHz */
95 { .n = 600, .m = 12, .p = 0, .cpcon = 8 }, /* OSC: 12.0 MHz */
96 { .n = 600, .m = 26, .p = 0, .cpcon = 8 }, /* OSC: 26.0 MHz */
97 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 38.4 MHz (N/A) */
98 { .n = 0, .m = 0, .p = 0, .cpcon = 0 }, /* OSC: 48.0 MHz (N/A) */
103 * Register Field Bits Width
104 * ------------------------------
105 * PLLX_BASE p 23:20 4
106 * PLLX_BASE n 15: 8 8
110 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
111 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
112 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
113 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
114 { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
115 { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
121 * Register Field Bits Width
122 * ------------------------------
123 * PLLX_BASE p 23:20 4
124 * PLLX_BASE n 15: 8 8
128 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz */
129 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz */
130 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz */
131 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz */
132 { .n = 0, .m = 0, .p = 0 }, /* OSC: 38.4 MHz (N/A) */
133 { .n = 0, .m = 0, .p = 0 }, /* OSC: 48.0 MHz (N/A) */
139 * Register Field Bits Width
140 * ------------------------------
141 * PLLX_BASE p 24:20 5
142 * PLLX_BASE n 15: 8 8
146 { .n = 108, .m = 1, .p = 1 }, /* OSC: 13.0 MHz = 702 MHz*/
147 { .n = 73, .m = 1, .p = 1 }, /* OSC: 19.2 MHz = 700.8 MHz*/
148 { .n = 116, .m = 1, .p = 1 }, /* OSC: 12.0 MHz = 696 MHz*/
149 { .n = 108, .m = 2, .p = 1 }, /* OSC: 26.0 MHz = 702 MHz*/
150 { .n = 36, .m = 1, .p = 1 }, /* OSC: 38.4 MHz = 691.2 MHz */
151 { .n = 58, .m = 2, .p = 1 }, /* OSC: 48.0 MHz = 696 MHz */
155 static inline void pllx_set_iddq(void)
157 #if defined(CONFIG_TEGRA124) || defined(CONFIG_TEGRA210)
158 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
160 debug("%s entry\n", __func__);
163 reg = readl(&clkrst->crc_pllx_misc3);
164 reg &= ~PLLX_IDDQ_MASK;
165 writel(reg, &clkrst->crc_pllx_misc3);
167 debug("%s: IDDQ: PLLX IDDQ = 0x%08X\n", __func__,
168 readl(&clkrst->crc_pllx_misc3));
172 int pllx_set_rate(struct clk_pll_simple *pll , u32 divn, u32 divm,
175 struct clk_pll_info *pllinfo = &tegra_pll_info_table[CLOCK_ID_XCPU];
176 int chip = tegra_get_chip();
178 debug("%s entry\n", __func__);
180 /* If PLLX is already enabled, just return */
181 if (readl(&pll->pll_base) & PLL_ENABLE_MASK) {
182 debug("%s: PLLX already enabled, returning\n", __func__);
188 /* Set BYPASS, m, n and p to PLLX_BASE */
189 reg = PLL_BYPASS_MASK | (divm << pllinfo->m_shift);
190 reg |= (divn << pllinfo->n_shift) | (divp << pllinfo->p_shift);
191 writel(reg, &pll->pll_base);
193 /* Set cpcon to PLLX_MISC */
194 if (chip == CHIPID_TEGRA20 || chip == CHIPID_TEGRA30)
195 reg = (cpcon << pllinfo->kcp_shift);
200 * TODO(twarren@nvidia.com) Check which SoCs use DCCON
201 * and add to pllinfo table if needed!
203 /* Set dccon to PLLX_MISC if freq > 600MHz */
205 reg |= (1 << PLL_DCCON_SHIFT);
206 writel(reg, &pll->pll_misc);
209 reg = readl(&pll->pll_base);
210 reg &= ~PLL_BYPASS_MASK;
211 writel(reg, &pll->pll_base);
212 debug("%s: base = 0x%08X\n", __func__, reg);
214 /* Set lock_enable to PLLX_MISC if lock_ena is valid (i.e. 0-31) */
215 reg = readl(&pll->pll_misc);
216 if (pllinfo->lock_ena < 32)
217 reg |= (1 << pllinfo->lock_ena);
218 writel(reg, &pll->pll_misc);
219 debug("%s: misc = 0x%08X\n", __func__, reg);
221 /* Enable PLLX last, once it's all configured */
222 reg = readl(&pll->pll_base);
223 reg |= PLL_ENABLE_MASK;
224 writel(reg, &pll->pll_base);
225 debug("%s: base final = 0x%08X\n", __func__, reg);
232 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
233 struct clk_pll_simple *pll = &clkrst->crc_pll_simple[SIMPLE_PLLX];
234 int soc_type, sku_info, chip_sku;
235 enum clock_osc_freq osc;
236 struct clk_pll_table *sel;
237 debug("%s entry\n", __func__);
239 /* get SOC (chip) type */
240 soc_type = tegra_get_chip();
241 debug("%s: SoC = 0x%02X\n", __func__, soc_type);
244 sku_info = tegra_get_sku_info();
245 debug("%s: SKU info byte = 0x%02X\n", __func__, sku_info);
247 /* get chip SKU, combo of the above info */
248 chip_sku = tegra_get_chip_sku();
249 debug("%s: Chip SKU = %d\n", __func__, chip_sku);
252 osc = clock_get_osc_freq();
253 debug("%s: osc = %d\n", __func__, osc);
256 sel = &tegra_pll_x_table[chip_sku][osc];
257 pllx_set_rate(pll, sel->n, sel->m, sel->p, sel->cpcon);
260 void enable_cpu_clock(int enable)
262 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
264 debug("%s entry\n", __func__);
268 * Regardless of whether the request is to enable or disable the CPU
269 * clock, every processor in the CPU complex except the master (CPU 0)
270 * will have it's clock stopped because the AVP only talks to the
275 /* Initialize PLLX */
278 /* Wait until all clocks are stable */
279 udelay(PLL_STABILIZATION_DELAY);
281 writel(CCLK_BURST_POLICY, &clkrst->crc_cclk_brst_pol);
282 writel(SUPER_CCLK_DIVIDER, &clkrst->crc_super_cclk_div);
286 * Read the register containing the individual CPU clock enables and
287 * always stop the clocks to CPUs > 0.
289 clk = readl(&clkrst->crc_clk_cpu_cmplx);
290 clk |= 1 << CPU1_CLK_STP_SHIFT;
291 if (get_num_cpus() == 4)
292 clk |= (1 << CPU2_CLK_STP_SHIFT) + (1 << CPU3_CLK_STP_SHIFT);
294 /* Stop/Unstop the CPU clock */
295 clk &= ~CPU0_CLK_STP_MASK;
296 clk |= !enable << CPU0_CLK_STP_SHIFT;
297 writel(clk, &clkrst->crc_clk_cpu_cmplx);
299 clock_enable(PERIPH_ID_CPU);
302 static int is_cpu_powered(void)
304 return (tegra_pmc_readl(offsetof(struct pmc_ctlr,
305 pmc_pwrgate_status)) & CPU_PWRED) ? 1 : 0;
308 static void remove_cpu_io_clamps(void)
311 debug("%s entry\n", __func__);
313 /* Remove the clamps on the CPU I/O signals */
314 reg = tegra_pmc_readl(offsetof(struct pmc_ctlr, pmc_remove_clamping));
316 tegra_pmc_writel(reg, offsetof(struct pmc_ctlr, pmc_remove_clamping));
318 /* Give I/O signals time to stabilize */
319 udelay(IO_STABILIZATION_DELAY);
322 void powerup_cpu(void)
325 int timeout = IO_STABILIZATION_DELAY;
326 debug("%s entry\n", __func__);
328 if (!is_cpu_powered()) {
329 /* Toggle the CPU power state (OFF -> ON) */
330 reg = tegra_pmc_readl(offsetof(struct pmc_ctlr,
331 pmc_pwrgate_toggle));
334 tegra_pmc_writel(reg,
335 offsetof(struct pmc_ctlr,
336 pmc_pwrgate_toggle));
338 /* Wait for the power to come up */
339 while (!is_cpu_powered()) {
341 printf("CPU failed to power up!\n");
347 * Remove the I/O clamps from CPU power partition.
348 * Recommended only on a Warm boot, if the CPU partition gets
349 * power gated. Shouldn't cause any harm when called after a
350 * cold boot according to HW, probably just redundant.
352 remove_cpu_io_clamps();
356 void reset_A9_cpu(int reset)
359 * NOTE: Regardless of whether the request is to hold the CPU in reset
360 * or take it out of reset, every processor in the CPU complex
361 * except the master (CPU 0) will be held in reset because the
362 * AVP only talks to the master. The AVP does not know that there
363 * are multiple processors in the CPU complex.
365 int mask = crc_rst_cpu | crc_rst_de | crc_rst_debug;
366 int num_cpus = get_num_cpus();
369 debug("%s entry\n", __func__);
370 /* Hold CPUs 1 onwards in reset, and CPU 0 if asked */
371 for (cpu = 1; cpu < num_cpus; cpu++)
372 reset_cmplx_set_enable(cpu, mask, 1);
373 reset_cmplx_set_enable(0, mask, reset);
375 /* Enable/Disable master CPU reset */
376 reset_set_enable(PERIPH_ID_CPU, reset);
379 void clock_enable_coresight(int enable)
383 debug("%s entry\n", __func__);
384 clock_set_enable(PERIPH_ID_CORESIGHT, enable);
385 reset_set_enable(PERIPH_ID_CORESIGHT, !enable);
389 * Put CoreSight on PLLP_OUT0 and divide it down as per
390 * PLLP base frequency based on SoC type (T20/T30+).
391 * Clock divider request would setup CSITE clock as 144MHz
392 * for PLLP base 216MHz and 204MHz for PLLP base 408MHz
394 src = CLK_DIVIDER(NVBL_PLLP_KHZ, CSITE_KHZ);
395 clock_ll_set_source_divisor(PERIPH_ID_CSI, 0, src);
397 /* Unlock the CPU CoreSight interfaces */
398 rst = CORESIGHT_UNLOCK;
399 writel(rst, CSITE_CPU_DBG0_LAR);
400 writel(rst, CSITE_CPU_DBG1_LAR);
401 if (get_num_cpus() == 4) {
402 writel(rst, CSITE_CPU_DBG2_LAR);
403 writel(rst, CSITE_CPU_DBG3_LAR);
410 debug("%s entry\n", __func__);
413 writel(HALT_COP_EVENT_JTAG | (FLOW_MODE_STOP << 29),
414 FLOW_CTLR_HALT_COP_EVENTS);