1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2010-2019, NVIDIA CORPORATION. All rights reserved.
6 /* Tegra SoC common clock control functions */
15 #include <asm/arch/clock.h>
16 #include <asm/arch/tegra.h>
17 #include <asm/arch-tegra/ap.h>
18 #include <asm/arch-tegra/clk_rst.h>
19 #include <asm/arch-tegra/pmc.h>
20 #include <asm/arch-tegra/timer.h>
21 #include <linux/delay.h>
24 * This is our record of the current clock rate of each clock. We don't
25 * fill all of these in since we are only really interested in clocks which
28 static unsigned pll_rate[CLOCK_ID_COUNT];
31 * The oscillator frequency is fixed to one of four set values. Based on this
32 * the other clocks are set up appropriately.
34 static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
43 /* return 1 if a peripheral ID is in range */
44 #define clock_type_id_isvalid(id) ((id) >= 0 && \
45 (id) < CLOCK_TYPE_COUNT)
47 char pllp_valid = 1; /* PLLP is set up correctly */
49 /* return 1 if a periphc_internal_id is in range */
50 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
53 /* number of clock outputs of a PLL */
54 static const u8 pll_num_clkouts[] = {
63 int clock_get_osc_bypass(void)
65 struct clk_rst_ctlr *clkrst =
66 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
69 reg = readl(&clkrst->crc_osc_ctrl);
70 return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
73 /* Returns a pointer to the registers of the given pll */
74 static struct clk_pll *get_pll(enum clock_id clkid)
76 struct clk_rst_ctlr *clkrst =
77 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
79 assert(clock_id_is_pll(clkid));
80 if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
81 debug("%s: Invalid PLL %d\n", __func__, clkid);
84 return &clkrst->crc_pll[clkid];
87 __weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
92 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
93 u32 *divp, u32 *cpcon, u32 *lfcon)
95 struct clk_pll *pll = get_pll(clkid);
96 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
99 assert(clkid != CLOCK_ID_USB);
101 /* Safety check, adds to code size but is small */
102 if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
104 data = readl(&pll->pll_base);
105 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask;
106 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask;
107 *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask;
108 data = readl(&pll->pll_misc);
109 /* NOTE: On T210, cpcon/lfcon no longer exist, moved to KCP/KVCO */
110 *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask;
111 *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask;
116 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
117 u32 divp, u32 cpcon, u32 lfcon)
119 struct clk_pll *pll = NULL;
120 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
121 struct clk_pll_simple *simple_pll = NULL;
124 if (clkid < (enum clock_id)TEGRA_CLK_PLLS) {
125 pll = get_pll(clkid);
127 simple_pll = clock_get_simple_pll(clkid);
129 debug("%s: Uknown simple PLL %d\n", __func__, clkid);
135 * pllinfo has the m/n/p and kcp/kvco mask and shift
136 * values for all of the PLLs used in U-Boot, with any
137 * SoC differences accounted for.
139 * Preserve EN_LOCKDET, etc.
142 misc_data = readl(&pll->pll_misc);
144 misc_data = readl(&simple_pll->pll_misc);
145 misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
146 misc_data |= cpcon << pllinfo->kcp_shift;
147 misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift);
148 misc_data |= lfcon << pllinfo->kvco_shift;
150 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift);
151 data |= divp << pllinfo->p_shift;
152 data |= (1 << PLL_ENABLE_SHIFT); /* BYPASS s/b 0 already */
155 writel(misc_data, &pll->pll_misc);
156 writel(data, &pll->pll_base);
158 writel(misc_data, &simple_pll->pll_misc);
159 writel(data, &simple_pll->pll_base);
162 /* calculate the stable time */
163 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
166 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
169 u32 *reg = get_periph_source_reg(periph_id);
174 value &= ~OUT_CLK_SOURCE_31_30_MASK;
175 value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
177 value &= ~OUT_CLK_DIVISOR_MASK;
178 value |= divisor << OUT_CLK_DIVISOR_SHIFT;
183 int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
186 u32 *reg = get_periph_source_reg(periph_id);
189 case MASK_BITS_31_30:
190 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
191 source << OUT_CLK_SOURCE_31_30_SHIFT);
194 case MASK_BITS_31_29:
195 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
196 source << OUT_CLK_SOURCE_31_29_SHIFT);
199 case MASK_BITS_31_28:
200 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
201 source << OUT_CLK_SOURCE_31_28_SHIFT);
211 static int clock_ll_get_source_bits(enum periph_id periph_id, int mux_bits)
213 u32 *reg = get_periph_source_reg(periph_id);
214 u32 val = readl(reg);
217 case MASK_BITS_31_30:
218 val >>= OUT_CLK_SOURCE_31_30_SHIFT;
219 val &= OUT_CLK_SOURCE_31_30_MASK;
221 case MASK_BITS_31_29:
222 val >>= OUT_CLK_SOURCE_31_29_SHIFT;
223 val &= OUT_CLK_SOURCE_31_29_MASK;
225 case MASK_BITS_31_28:
226 val >>= OUT_CLK_SOURCE_31_28_SHIFT;
227 val &= OUT_CLK_SOURCE_31_28_MASK;
234 void clock_ll_set_source(enum periph_id periph_id, unsigned source)
236 clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
240 * Given the parent's rate and the required rate for the children, this works
241 * out the peripheral clock divider to use, in 7.1 binary format.
243 * @param divider_bits number of divider bits (8 or 16)
244 * @param parent_rate clock rate of parent clock in Hz
245 * @param rate required clock rate for this clock
246 * @return divider which should be used
248 static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
251 u64 divider = parent_rate * 2;
252 unsigned max_divider = 1 << divider_bits;
255 do_div(divider, rate);
257 if ((s64)divider - 2 < 0)
260 if ((s64)divider - 2 >= max_divider)
266 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
268 struct clk_pll *pll = get_pll(clkid);
269 int data = 0, div = 0, offset = 0;
271 if (!clock_id_is_pll(clkid))
274 if (pllout + 1 > pll_num_clkouts[clkid])
277 div = clk_get_divider(8, pll_rate[clkid], rate);
282 /* out2 and out4 are in the high part of the register */
283 if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
286 data = (div << PLL_OUT_RATIO_SHIFT) |
287 PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
288 clrsetbits_le32(&pll->pll_out[pllout >> 1],
289 PLL_OUT_RATIO_MASK << offset, data << offset);
295 * Given the parent's rate and the divider in 7.1 format, this works out the
296 * resulting peripheral clock rate.
298 * @param parent_rate clock rate of parent clock in Hz
299 * @param divider which should be used in 7.1 format
300 * @return effective clock rate of peripheral
302 static unsigned long get_rate_from_divider(unsigned long parent_rate,
307 rate = (u64)parent_rate * 2;
308 do_div(rate, divider + 2);
312 unsigned long clock_get_periph_rate(enum periph_id periph_id,
313 enum clock_id parent)
315 u32 *reg = get_periph_source_reg(periph_id);
316 unsigned parent_rate = pll_rate[parent];
317 int div = (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT;
320 case PERIPH_ID_UART1:
321 case PERIPH_ID_UART2:
322 case PERIPH_ID_UART3:
323 case PERIPH_ID_UART4:
324 case PERIPH_ID_UART5:
325 #ifdef CONFIG_TEGRA20
326 /* There's no divider for these clocks in this SoC. */
330 * This undoes the +2 in get_rate_from_divider() which I
331 * believe is incorrect. Ideally we would fix
332 * get_rate_from_divider(), but... Removing the +2 from
333 * get_rate_from_divider() would probably require remove the -2
334 * from the tail of clk_get_divider() since I believe that's
335 * only there to invert get_rate_from_divider()'s +2. Observe
336 * how find_best_divider() uses those two functions together.
337 * However, doing so breaks other stuff, such as Seaboard's
338 * display, likely due to clock_set_pllout()'s call to
339 * clk_get_divider(). Attempting to fix that by making
340 * clock_set_pllout() subtract 2 from clk_get_divider()'s
341 * return value doesn't help. In summary this clock driver is
342 * quite broken but I'm afraid I have no idea how to fix it
343 * without completely replacing it.
345 * Be careful to avoid a divide by zero error.
355 return get_rate_from_divider(parent_rate, div);
359 * Find the best available 7.1 format divisor given a parent clock rate and
360 * required child clock rate. This function assumes that a second-stage
361 * divisor is available which can divide by powers of 2 from 1 to 256.
363 * @param divider_bits number of divider bits (8 or 16)
364 * @param parent_rate clock rate of parent clock in Hz
365 * @param rate required clock rate for this clock
366 * @param extra_div value for the second-stage divisor (not set if this
367 * function returns -1.
368 * @return divider which should be used, or -1 if nothing is valid
371 static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
372 unsigned long rate, int *extra_div)
375 int best_divider = -1;
376 int best_error = rate;
378 /* try dividers from 1 to 256 and find closest match */
379 for (shift = 0; shift <= 8 && best_error > 0; shift++) {
380 unsigned divided_parent = parent_rate >> shift;
381 int divider = clk_get_divider(divider_bits, divided_parent,
383 unsigned effective_rate = get_rate_from_divider(divided_parent,
385 int error = rate - effective_rate;
387 /* Given a valid divider, look for the lowest error */
388 if (divider != -1 && error < best_error) {
390 *extra_div = 1 << shift;
391 best_divider = divider;
395 /* return what we found - *extra_div will already be set */
400 * Adjust peripheral PLL to use the given divider and source.
402 * @param periph_id peripheral to adjust
403 * @param source Source number (0-3 or 0-7)
404 * @param mux_bits Number of mux bits (2 or 4)
405 * @param divider Required divider in 7.1 or 15.1 format
406 * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
407 * for this peripheral)
409 static int adjust_periph_pll(enum periph_id periph_id, int source,
410 int mux_bits, unsigned divider)
412 u32 *reg = get_periph_source_reg(periph_id);
414 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
415 divider << OUT_CLK_DIVISOR_SHIFT);
418 /* work out the source clock and set it */
422 clock_ll_set_source_bits(periph_id, mux_bits, source);
428 enum clock_id clock_get_periph_parent(enum periph_id periph_id)
430 int err, mux_bits, divider_bits, type;
433 err = get_periph_clock_info(periph_id, &mux_bits, ÷r_bits, &type);
435 return CLOCK_ID_NONE;
437 source = clock_ll_get_source_bits(periph_id, mux_bits);
439 return get_periph_clock_id(periph_id, source);
442 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
443 enum clock_id parent, unsigned rate, int *extra_div)
445 unsigned effective_rate;
446 int mux_bits, divider_bits, source;
450 /* work out the source clock and set it */
451 source = get_periph_clock_source(periph_id, parent, &mux_bits,
454 divider = find_best_divider(divider_bits, pll_rate[parent],
459 assert(divider >= 0);
460 if (adjust_periph_pll(periph_id, source, mux_bits, divider))
462 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
463 get_periph_source_reg(periph_id),
464 readl(get_periph_source_reg(periph_id)));
466 /* Check what we ended up with. This shouldn't matter though */
467 effective_rate = clock_get_periph_rate(periph_id, parent);
469 effective_rate /= *extra_div;
470 if (rate != effective_rate)
471 debug("Requested clock rate %u not honored (got %u)\n",
472 rate, effective_rate);
473 return effective_rate;
476 unsigned clock_start_periph_pll(enum periph_id periph_id,
477 enum clock_id parent, unsigned rate)
479 unsigned effective_rate;
481 reset_set_enable(periph_id, 1);
482 clock_enable(periph_id);
485 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
488 reset_set_enable(periph_id, 0);
489 return effective_rate;
492 void clock_enable(enum periph_id clkid)
494 clock_set_enable(clkid, 1);
497 void clock_disable(enum periph_id clkid)
499 clock_set_enable(clkid, 0);
502 void reset_periph(enum periph_id periph_id, int us_delay)
504 /* Put peripheral into reset */
505 reset_set_enable(periph_id, 1);
509 reset_set_enable(periph_id, 0);
514 void reset_cmplx_set_enable(int cpu, int which, int reset)
516 struct clk_rst_ctlr *clkrst =
517 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
520 /* Form the mask, which depends on the cpu chosen (2 or 4) */
521 assert(cpu >= 0 && cpu < MAX_NUM_CPU);
524 /* either enable or disable those reset for that CPU */
526 writel(mask, &clkrst->crc_cpu_cmplx_set);
528 writel(mask, &clkrst->crc_cpu_cmplx_clr);
531 unsigned int __weak clk_m_get_rate(unsigned int parent_rate)
536 unsigned clock_get_rate(enum clock_id clkid)
540 u64 parent_rate, rate;
541 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
543 parent_rate = osc_freq[clock_get_osc_freq()];
544 if (clkid == CLOCK_ID_OSC)
547 if (clkid == CLOCK_ID_CLK_M)
548 return clk_m_get_rate(parent_rate);
550 pll = get_pll(clkid);
553 base = readl(&pll->pll_base);
555 rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask);
556 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask;
558 * PLLU uses p_mask/p_shift for VCO on all but T210,
559 * T210 uses normal DIVP. Handled in pllinfo table.
561 #ifdef CONFIG_TEGRA210
563 * PLLP's primary output (pllP_out0) on T210 is the VCO, and divp is
564 * not applied. pllP_out2 does have divp applied. All other pllP_outN
565 * are divided down from pllP_out0. We only support pllP_out0 in
566 * U-Boot at the time of writing this comment.
568 if (clkid != CLOCK_ID_PERIPH)
570 divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask;
576 * Set the output frequency you want for each PLL clock.
577 * PLL output frequencies are programmed by setting their N, M and P values.
578 * The governing equations are:
579 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
580 * where Fo is the output frequency from the PLL.
581 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
582 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
583 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
585 * @param n PLL feedback divider(DIVN)
586 * @param m PLL input divider(DIVN)
587 * @param p post divider(DIVP)
588 * @param cpcon base PLL charge pump(CPCON)
589 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
590 * be overridden), 1 if PLL is already correct
592 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
594 u32 base_reg, misc_reg;
596 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
598 pll = get_pll(clkid);
600 base_reg = readl(&pll->pll_base);
602 /* Set BYPASS, m, n and p to PLL_BASE */
603 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift);
604 base_reg |= m << pllinfo->m_shift;
606 base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift);
607 base_reg |= n << pllinfo->n_shift;
609 base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift);
610 base_reg |= p << pllinfo->p_shift;
612 if (clkid == CLOCK_ID_PERIPH) {
614 * If the PLL is already set up, check that it is correct
615 * and record this info for clock_verify() to check.
617 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
618 base_reg |= PLL_ENABLE_MASK;
619 if (base_reg != readl(&pll->pll_base))
621 return pllp_valid ? 1 : -1;
623 base_reg |= PLL_BASE_OVRRIDE_MASK;
626 base_reg |= PLL_BYPASS_MASK;
627 writel(base_reg, &pll->pll_base);
629 /* Set cpcon (KCP) to PLL_MISC */
630 misc_reg = readl(&pll->pll_misc);
631 misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
632 misc_reg |= cpcon << pllinfo->kcp_shift;
633 writel(misc_reg, &pll->pll_misc);
636 base_reg |= PLL_ENABLE_MASK;
637 writel(base_reg, &pll->pll_base);
640 base_reg &= ~PLL_BYPASS_MASK;
641 writel(base_reg, &pll->pll_base);
646 void clock_ll_start_uart(enum periph_id periph_id)
648 /* Assert UART reset and enable clock */
649 reset_set_enable(periph_id, 1);
650 clock_enable(periph_id);
651 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
656 /* De-assert reset to UART */
657 reset_set_enable(periph_id, 0);
660 #if CONFIG_IS_ENABLED(OF_CONTROL)
661 int clock_decode_periph_id(struct udevice *dev)
667 err = dev_read_u32_array(dev, "clocks", cell, ARRAY_SIZE(cell));
670 id = clk_id_to_periph_id(cell[1]);
671 assert(clock_periph_id_isvalid(id));
674 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
676 int clock_verify(void)
678 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
679 u32 reg = readl(&pll->pll_base);
682 printf("Warning: PLLP %x is not correct\n", reg);
685 debug("PLLP %x is correct\n", reg);
689 void clock_init(void)
693 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
694 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
695 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
696 pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB);
697 pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);
698 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
699 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
700 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
701 pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M);
703 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
704 debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]);
705 debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
706 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
707 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
708 debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]);
709 debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
710 debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
712 for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) {
713 enum periph_id periph_id;
714 enum clock_id parent;
715 int source, mux_bits, divider_bits;
717 periph_id = periph_clk_init_table[i].periph_id;
718 parent = periph_clk_init_table[i].parent_clock_id;
720 source = get_periph_clock_source(periph_id, parent, &mux_bits,
722 clock_ll_set_source_bits(periph_id, mux_bits, source);
726 static void set_avp_clock_source(u32 src)
728 struct clk_rst_ctlr *clkrst =
729 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
732 val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
733 (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
734 (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
735 (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
736 (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
737 writel(val, &clkrst->crc_sclk_brst_pol);
742 * This function is useful on Tegra30, and any later SoCs that have compatible
743 * PLLP configuration registers.
744 * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
746 void tegra30_set_up_pllp(void)
748 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
752 * Based on the Tegra TRM, the system clock (which is the AVP clock) can
753 * run up to 275MHz. On power on, the default sytem clock source is set
754 * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
755 * 408MHz which is beyond system clock's upper limit.
757 * The fix is to set the system clock to CLK_M before initializing PLLP,
758 * and then switch back to PLLP_OUT4, which has an appropriate divider
759 * configured, after PLLP has been configured
761 set_avp_clock_source(SCLK_SOURCE_CLKM);
764 * PLLP output frequency set to 408Mhz
765 * PLLC output frequency set to 228Mhz
767 switch (clock_get_osc_freq()) {
768 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
769 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
770 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
773 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
774 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
775 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
778 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
779 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
780 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
782 case CLOCK_OSC_FREQ_19_2:
785 * These are not supported. It is too early to print a
786 * message and the UART likely won't work anyway due to the
787 * oscillator being wrong.
792 /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
795 /* Assert RSTN before enable */
796 reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
797 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
798 /* Set divisor and reenable */
799 reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
800 | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
801 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
802 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
803 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
806 /* Assert RSTN before enable */
807 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
808 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
809 /* Set divisor and reenable */
810 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
811 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
812 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
813 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
814 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
816 set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
819 int clock_external_output(int clk_id)
823 if (clk_id >= 1 && clk_id <= 3) {
824 val = tegra_pmc_readl(offsetof(struct pmc_ctlr,
826 val |= 1 << (2 + (clk_id - 1) * 8);
827 tegra_pmc_writel(val,
828 offsetof(struct pmc_ctlr,
832 printf("%s: Unknown output clock id %d\n", __func__, clk_id);
839 __weak bool clock_early_init_done(void)