1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2010-2015, NVIDIA CORPORATION. All rights reserved.
6 /* Tegra SoC common clock control functions */
13 #include <asm/arch/clock.h>
14 #include <asm/arch/tegra.h>
15 #include <asm/arch-tegra/ap.h>
16 #include <asm/arch-tegra/clk_rst.h>
17 #include <asm/arch-tegra/pmc.h>
18 #include <asm/arch-tegra/timer.h>
21 * This is our record of the current clock rate of each clock. We don't
22 * fill all of these in since we are only really interested in clocks which
25 static unsigned pll_rate[CLOCK_ID_COUNT];
28 * The oscillator frequency is fixed to one of four set values. Based on this
29 * the other clocks are set up appropriately.
31 static unsigned osc_freq[CLOCK_OSC_FREQ_COUNT] = {
40 /* return 1 if a peripheral ID is in range */
41 #define clock_type_id_isvalid(id) ((id) >= 0 && \
42 (id) < CLOCK_TYPE_COUNT)
44 char pllp_valid = 1; /* PLLP is set up correctly */
46 /* return 1 if a periphc_internal_id is in range */
47 #define periphc_internal_id_isvalid(id) ((id) >= 0 && \
50 /* number of clock outputs of a PLL */
51 static const u8 pll_num_clkouts[] = {
60 int clock_get_osc_bypass(void)
62 struct clk_rst_ctlr *clkrst =
63 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
66 reg = readl(&clkrst->crc_osc_ctrl);
67 return (reg & OSC_XOBP_MASK) >> OSC_XOBP_SHIFT;
70 /* Returns a pointer to the registers of the given pll */
71 static struct clk_pll *get_pll(enum clock_id clkid)
73 struct clk_rst_ctlr *clkrst =
74 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
76 assert(clock_id_is_pll(clkid));
77 if (clkid >= (enum clock_id)TEGRA_CLK_PLLS) {
78 debug("%s: Invalid PLL %d\n", __func__, clkid);
81 return &clkrst->crc_pll[clkid];
84 __weak struct clk_pll_simple *clock_get_simple_pll(enum clock_id clkid)
89 int clock_ll_read_pll(enum clock_id clkid, u32 *divm, u32 *divn,
90 u32 *divp, u32 *cpcon, u32 *lfcon)
92 struct clk_pll *pll = get_pll(clkid);
93 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
96 assert(clkid != CLOCK_ID_USB);
98 /* Safety check, adds to code size but is small */
99 if (!clock_id_is_pll(clkid) || clkid == CLOCK_ID_USB)
101 data = readl(&pll->pll_base);
102 *divm = (data >> pllinfo->m_shift) & pllinfo->m_mask;
103 *divn = (data >> pllinfo->n_shift) & pllinfo->n_mask;
104 *divp = (data >> pllinfo->p_shift) & pllinfo->p_mask;
105 data = readl(&pll->pll_misc);
106 /* NOTE: On T210, cpcon/lfcon no longer exist, moved to KCP/KVCO */
107 *cpcon = (data >> pllinfo->kcp_shift) & pllinfo->kcp_mask;
108 *lfcon = (data >> pllinfo->kvco_shift) & pllinfo->kvco_mask;
113 unsigned long clock_start_pll(enum clock_id clkid, u32 divm, u32 divn,
114 u32 divp, u32 cpcon, u32 lfcon)
116 struct clk_pll *pll = NULL;
117 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
118 struct clk_pll_simple *simple_pll = NULL;
121 if (clkid < (enum clock_id)TEGRA_CLK_PLLS) {
122 pll = get_pll(clkid);
124 simple_pll = clock_get_simple_pll(clkid);
126 debug("%s: Uknown simple PLL %d\n", __func__, clkid);
132 * pllinfo has the m/n/p and kcp/kvco mask and shift
133 * values for all of the PLLs used in U-Boot, with any
134 * SoC differences accounted for.
136 * Preserve EN_LOCKDET, etc.
139 misc_data = readl(&pll->pll_misc);
141 misc_data = readl(&simple_pll->pll_misc);
142 misc_data &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
143 misc_data |= cpcon << pllinfo->kcp_shift;
144 misc_data &= ~(pllinfo->kvco_mask << pllinfo->kvco_shift);
145 misc_data |= lfcon << pllinfo->kvco_shift;
147 data = (divm << pllinfo->m_shift) | (divn << pllinfo->n_shift);
148 data |= divp << pllinfo->p_shift;
149 data |= (1 << PLL_ENABLE_SHIFT); /* BYPASS s/b 0 already */
152 writel(misc_data, &pll->pll_misc);
153 writel(data, &pll->pll_base);
155 writel(misc_data, &simple_pll->pll_misc);
156 writel(data, &simple_pll->pll_base);
159 /* calculate the stable time */
160 return timer_get_us() + CLOCK_PLL_STABLE_DELAY_US;
163 void clock_ll_set_source_divisor(enum periph_id periph_id, unsigned source,
166 u32 *reg = get_periph_source_reg(periph_id);
171 value &= ~OUT_CLK_SOURCE_31_30_MASK;
172 value |= source << OUT_CLK_SOURCE_31_30_SHIFT;
174 value &= ~OUT_CLK_DIVISOR_MASK;
175 value |= divisor << OUT_CLK_DIVISOR_SHIFT;
180 int clock_ll_set_source_bits(enum periph_id periph_id, int mux_bits,
183 u32 *reg = get_periph_source_reg(periph_id);
186 case MASK_BITS_31_30:
187 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_30_MASK,
188 source << OUT_CLK_SOURCE_31_30_SHIFT);
191 case MASK_BITS_31_29:
192 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_29_MASK,
193 source << OUT_CLK_SOURCE_31_29_SHIFT);
196 case MASK_BITS_31_28:
197 clrsetbits_le32(reg, OUT_CLK_SOURCE_31_28_MASK,
198 source << OUT_CLK_SOURCE_31_28_SHIFT);
208 static int clock_ll_get_source_bits(enum periph_id periph_id, int mux_bits)
210 u32 *reg = get_periph_source_reg(periph_id);
211 u32 val = readl(reg);
214 case MASK_BITS_31_30:
215 val >>= OUT_CLK_SOURCE_31_30_SHIFT;
216 val &= OUT_CLK_SOURCE_31_30_MASK;
218 case MASK_BITS_31_29:
219 val >>= OUT_CLK_SOURCE_31_29_SHIFT;
220 val &= OUT_CLK_SOURCE_31_29_MASK;
222 case MASK_BITS_31_28:
223 val >>= OUT_CLK_SOURCE_31_28_SHIFT;
224 val &= OUT_CLK_SOURCE_31_28_MASK;
231 void clock_ll_set_source(enum periph_id periph_id, unsigned source)
233 clock_ll_set_source_bits(periph_id, MASK_BITS_31_30, source);
237 * Given the parent's rate and the required rate for the children, this works
238 * out the peripheral clock divider to use, in 7.1 binary format.
240 * @param divider_bits number of divider bits (8 or 16)
241 * @param parent_rate clock rate of parent clock in Hz
242 * @param rate required clock rate for this clock
243 * @return divider which should be used
245 static int clk_get_divider(unsigned divider_bits, unsigned long parent_rate,
248 u64 divider = parent_rate * 2;
249 unsigned max_divider = 1 << divider_bits;
252 do_div(divider, rate);
254 if ((s64)divider - 2 < 0)
257 if ((s64)divider - 2 >= max_divider)
263 int clock_set_pllout(enum clock_id clkid, enum pll_out_id pllout, unsigned rate)
265 struct clk_pll *pll = get_pll(clkid);
266 int data = 0, div = 0, offset = 0;
268 if (!clock_id_is_pll(clkid))
271 if (pllout + 1 > pll_num_clkouts[clkid])
274 div = clk_get_divider(8, pll_rate[clkid], rate);
279 /* out2 and out4 are in the high part of the register */
280 if (pllout == PLL_OUT2 || pllout == PLL_OUT4)
283 data = (div << PLL_OUT_RATIO_SHIFT) |
284 PLL_OUT_OVRRIDE | PLL_OUT_CLKEN | PLL_OUT_RSTN;
285 clrsetbits_le32(&pll->pll_out[pllout >> 1],
286 PLL_OUT_RATIO_MASK << offset, data << offset);
292 * Given the parent's rate and the divider in 7.1 format, this works out the
293 * resulting peripheral clock rate.
295 * @param parent_rate clock rate of parent clock in Hz
296 * @param divider which should be used in 7.1 format
297 * @return effective clock rate of peripheral
299 static unsigned long get_rate_from_divider(unsigned long parent_rate,
304 rate = (u64)parent_rate * 2;
305 do_div(rate, divider + 2);
309 unsigned long clock_get_periph_rate(enum periph_id periph_id,
310 enum clock_id parent)
312 u32 *reg = get_periph_source_reg(periph_id);
313 unsigned parent_rate = pll_rate[parent];
314 int div = (readl(reg) & OUT_CLK_DIVISOR_MASK) >> OUT_CLK_DIVISOR_SHIFT;
317 case PERIPH_ID_UART1:
318 case PERIPH_ID_UART2:
319 case PERIPH_ID_UART3:
320 case PERIPH_ID_UART4:
321 case PERIPH_ID_UART5:
322 #ifdef CONFIG_TEGRA20
323 /* There's no divider for these clocks in this SoC. */
327 * This undoes the +2 in get_rate_from_divider() which I
328 * believe is incorrect. Ideally we would fix
329 * get_rate_from_divider(), but... Removing the +2 from
330 * get_rate_from_divider() would probably require remove the -2
331 * from the tail of clk_get_divider() since I believe that's
332 * only there to invert get_rate_from_divider()'s +2. Observe
333 * how find_best_divider() uses those two functions together.
334 * However, doing so breaks other stuff, such as Seaboard's
335 * display, likely due to clock_set_pllout()'s call to
336 * clk_get_divider(). Attempting to fix that by making
337 * clock_set_pllout() subtract 2 from clk_get_divider()'s
338 * return value doesn't help. In summary this clock driver is
339 * quite broken but I'm afraid I have no idea how to fix it
340 * without completely replacing it.
342 * Be careful to avoid a divide by zero error.
352 return get_rate_from_divider(parent_rate, div);
356 * Find the best available 7.1 format divisor given a parent clock rate and
357 * required child clock rate. This function assumes that a second-stage
358 * divisor is available which can divide by powers of 2 from 1 to 256.
360 * @param divider_bits number of divider bits (8 or 16)
361 * @param parent_rate clock rate of parent clock in Hz
362 * @param rate required clock rate for this clock
363 * @param extra_div value for the second-stage divisor (not set if this
364 * function returns -1.
365 * @return divider which should be used, or -1 if nothing is valid
368 static int find_best_divider(unsigned divider_bits, unsigned long parent_rate,
369 unsigned long rate, int *extra_div)
372 int best_divider = -1;
373 int best_error = rate;
375 /* try dividers from 1 to 256 and find closest match */
376 for (shift = 0; shift <= 8 && best_error > 0; shift++) {
377 unsigned divided_parent = parent_rate >> shift;
378 int divider = clk_get_divider(divider_bits, divided_parent,
380 unsigned effective_rate = get_rate_from_divider(divided_parent,
382 int error = rate - effective_rate;
384 /* Given a valid divider, look for the lowest error */
385 if (divider != -1 && error < best_error) {
387 *extra_div = 1 << shift;
388 best_divider = divider;
392 /* return what we found - *extra_div will already be set */
397 * Adjust peripheral PLL to use the given divider and source.
399 * @param periph_id peripheral to adjust
400 * @param source Source number (0-3 or 0-7)
401 * @param mux_bits Number of mux bits (2 or 4)
402 * @param divider Required divider in 7.1 or 15.1 format
403 * @return 0 if ok, -1 on error (requesting a parent clock which is not valid
404 * for this peripheral)
406 static int adjust_periph_pll(enum periph_id periph_id, int source,
407 int mux_bits, unsigned divider)
409 u32 *reg = get_periph_source_reg(periph_id);
411 clrsetbits_le32(reg, OUT_CLK_DIVISOR_MASK,
412 divider << OUT_CLK_DIVISOR_SHIFT);
415 /* work out the source clock and set it */
419 clock_ll_set_source_bits(periph_id, mux_bits, source);
425 enum clock_id clock_get_periph_parent(enum periph_id periph_id)
427 int err, mux_bits, divider_bits, type;
430 err = get_periph_clock_info(periph_id, &mux_bits, ÷r_bits, &type);
432 return CLOCK_ID_NONE;
434 source = clock_ll_get_source_bits(periph_id, mux_bits);
436 return get_periph_clock_id(periph_id, source);
439 unsigned clock_adjust_periph_pll_div(enum periph_id periph_id,
440 enum clock_id parent, unsigned rate, int *extra_div)
442 unsigned effective_rate;
443 int mux_bits, divider_bits, source;
447 /* work out the source clock and set it */
448 source = get_periph_clock_source(periph_id, parent, &mux_bits,
451 divider = find_best_divider(divider_bits, pll_rate[parent],
456 assert(divider >= 0);
457 if (adjust_periph_pll(periph_id, source, mux_bits, divider))
459 debug("periph %d, rate=%d, reg=%p = %x\n", periph_id, rate,
460 get_periph_source_reg(periph_id),
461 readl(get_periph_source_reg(periph_id)));
463 /* Check what we ended up with. This shouldn't matter though */
464 effective_rate = clock_get_periph_rate(periph_id, parent);
466 effective_rate /= *extra_div;
467 if (rate != effective_rate)
468 debug("Requested clock rate %u not honored (got %u)\n",
469 rate, effective_rate);
470 return effective_rate;
473 unsigned clock_start_periph_pll(enum periph_id periph_id,
474 enum clock_id parent, unsigned rate)
476 unsigned effective_rate;
478 reset_set_enable(periph_id, 1);
479 clock_enable(periph_id);
481 effective_rate = clock_adjust_periph_pll_div(periph_id, parent, rate,
484 reset_set_enable(periph_id, 0);
485 return effective_rate;
488 void clock_enable(enum periph_id clkid)
490 clock_set_enable(clkid, 1);
493 void clock_disable(enum periph_id clkid)
495 clock_set_enable(clkid, 0);
498 void reset_periph(enum periph_id periph_id, int us_delay)
500 /* Put peripheral into reset */
501 reset_set_enable(periph_id, 1);
505 reset_set_enable(periph_id, 0);
510 void reset_cmplx_set_enable(int cpu, int which, int reset)
512 struct clk_rst_ctlr *clkrst =
513 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
516 /* Form the mask, which depends on the cpu chosen (2 or 4) */
517 assert(cpu >= 0 && cpu < MAX_NUM_CPU);
520 /* either enable or disable those reset for that CPU */
522 writel(mask, &clkrst->crc_cpu_cmplx_set);
524 writel(mask, &clkrst->crc_cpu_cmplx_clr);
527 unsigned int __weak clk_m_get_rate(unsigned int parent_rate)
532 unsigned clock_get_rate(enum clock_id clkid)
536 u64 parent_rate, rate;
537 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
539 parent_rate = osc_freq[clock_get_osc_freq()];
540 if (clkid == CLOCK_ID_OSC)
543 if (clkid == CLOCK_ID_CLK_M)
544 return clk_m_get_rate(parent_rate);
546 pll = get_pll(clkid);
549 base = readl(&pll->pll_base);
551 rate = parent_rate * ((base >> pllinfo->n_shift) & pllinfo->n_mask);
552 divm = (base >> pllinfo->m_shift) & pllinfo->m_mask;
554 * PLLU uses p_mask/p_shift for VCO on all but T210,
555 * T210 uses normal DIVP. Handled in pllinfo table.
557 #ifdef CONFIG_TEGRA210
559 * PLLP's primary output (pllP_out0) on T210 is the VCO, and divp is
560 * not applied. pllP_out2 does have divp applied. All other pllP_outN
561 * are divided down from pllP_out0. We only support pllP_out0 in
562 * U-Boot at the time of writing this comment.
564 if (clkid != CLOCK_ID_PERIPH)
566 divm <<= (base >> pllinfo->p_shift) & pllinfo->p_mask;
572 * Set the output frequency you want for each PLL clock.
573 * PLL output frequencies are programmed by setting their N, M and P values.
574 * The governing equations are:
575 * VCO = (Fi / m) * n, Fo = VCO / (2^p)
576 * where Fo is the output frequency from the PLL.
577 * Example: Set the output frequency to 216Mhz(Fo) with 12Mhz OSC(Fi)
578 * 216Mhz = ((12Mhz / m) * n) / (2^p) so n=432,m=12,p=1
579 * Please see Tegra TRM section 5.3 to get the detail for PLL Programming
581 * @param n PLL feedback divider(DIVN)
582 * @param m PLL input divider(DIVN)
583 * @param p post divider(DIVP)
584 * @param cpcon base PLL charge pump(CPCON)
585 * @return 0 if ok, -1 on error (the requested PLL is incorrect and cannot
586 * be overridden), 1 if PLL is already correct
588 int clock_set_rate(enum clock_id clkid, u32 n, u32 m, u32 p, u32 cpcon)
590 u32 base_reg, misc_reg;
592 struct clk_pll_info *pllinfo = &tegra_pll_info_table[clkid];
594 pll = get_pll(clkid);
596 base_reg = readl(&pll->pll_base);
598 /* Set BYPASS, m, n and p to PLL_BASE */
599 base_reg &= ~(pllinfo->m_mask << pllinfo->m_shift);
600 base_reg |= m << pllinfo->m_shift;
602 base_reg &= ~(pllinfo->n_mask << pllinfo->n_shift);
603 base_reg |= n << pllinfo->n_shift;
605 base_reg &= ~(pllinfo->p_mask << pllinfo->p_shift);
606 base_reg |= p << pllinfo->p_shift;
608 if (clkid == CLOCK_ID_PERIPH) {
610 * If the PLL is already set up, check that it is correct
611 * and record this info for clock_verify() to check.
613 if (base_reg & PLL_BASE_OVRRIDE_MASK) {
614 base_reg |= PLL_ENABLE_MASK;
615 if (base_reg != readl(&pll->pll_base))
617 return pllp_valid ? 1 : -1;
619 base_reg |= PLL_BASE_OVRRIDE_MASK;
622 base_reg |= PLL_BYPASS_MASK;
623 writel(base_reg, &pll->pll_base);
625 /* Set cpcon (KCP) to PLL_MISC */
626 misc_reg = readl(&pll->pll_misc);
627 misc_reg &= ~(pllinfo->kcp_mask << pllinfo->kcp_shift);
628 misc_reg |= cpcon << pllinfo->kcp_shift;
629 writel(misc_reg, &pll->pll_misc);
632 base_reg |= PLL_ENABLE_MASK;
633 writel(base_reg, &pll->pll_base);
636 base_reg &= ~PLL_BYPASS_MASK;
637 writel(base_reg, &pll->pll_base);
642 void clock_ll_start_uart(enum periph_id periph_id)
644 /* Assert UART reset and enable clock */
645 reset_set_enable(periph_id, 1);
646 clock_enable(periph_id);
647 clock_ll_set_source(periph_id, 0); /* UARTx_CLK_SRC = 00, PLLP_OUT0 */
652 /* De-assert reset to UART */
653 reset_set_enable(periph_id, 0);
656 #if CONFIG_IS_ENABLED(OF_CONTROL)
657 int clock_decode_periph_id(struct udevice *dev)
663 err = dev_read_u32_array(dev, "clocks", cell, ARRAY_SIZE(cell));
666 id = clk_id_to_periph_id(cell[1]);
667 assert(clock_periph_id_isvalid(id));
670 #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
672 int clock_verify(void)
674 struct clk_pll *pll = get_pll(CLOCK_ID_PERIPH);
675 u32 reg = readl(&pll->pll_base);
678 printf("Warning: PLLP %x is not correct\n", reg);
681 debug("PLLP %x is correct\n", reg);
685 void clock_init(void)
689 pll_rate[CLOCK_ID_CGENERAL] = clock_get_rate(CLOCK_ID_CGENERAL);
690 pll_rate[CLOCK_ID_MEMORY] = clock_get_rate(CLOCK_ID_MEMORY);
691 pll_rate[CLOCK_ID_PERIPH] = clock_get_rate(CLOCK_ID_PERIPH);
692 pll_rate[CLOCK_ID_USB] = clock_get_rate(CLOCK_ID_USB);
693 pll_rate[CLOCK_ID_DISPLAY] = clock_get_rate(CLOCK_ID_DISPLAY);
694 pll_rate[CLOCK_ID_XCPU] = clock_get_rate(CLOCK_ID_XCPU);
695 pll_rate[CLOCK_ID_SFROM32KHZ] = 32768;
696 pll_rate[CLOCK_ID_OSC] = clock_get_rate(CLOCK_ID_OSC);
697 pll_rate[CLOCK_ID_CLK_M] = clock_get_rate(CLOCK_ID_CLK_M);
699 debug("Osc = %d\n", pll_rate[CLOCK_ID_OSC]);
700 debug("CLKM = %d\n", pll_rate[CLOCK_ID_CLK_M]);
701 debug("PLLC = %d\n", pll_rate[CLOCK_ID_CGENERAL]);
702 debug("PLLM = %d\n", pll_rate[CLOCK_ID_MEMORY]);
703 debug("PLLP = %d\n", pll_rate[CLOCK_ID_PERIPH]);
704 debug("PLLU = %d\n", pll_rate[CLOCK_ID_USB]);
705 debug("PLLD = %d\n", pll_rate[CLOCK_ID_DISPLAY]);
706 debug("PLLX = %d\n", pll_rate[CLOCK_ID_XCPU]);
708 for (i = 0; periph_clk_init_table[i].periph_id != -1; i++) {
709 enum periph_id periph_id;
710 enum clock_id parent;
711 int source, mux_bits, divider_bits;
713 periph_id = periph_clk_init_table[i].periph_id;
714 parent = periph_clk_init_table[i].parent_clock_id;
716 source = get_periph_clock_source(periph_id, parent, &mux_bits,
718 clock_ll_set_source_bits(periph_id, mux_bits, source);
722 static void set_avp_clock_source(u32 src)
724 struct clk_rst_ctlr *clkrst =
725 (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
728 val = (src << SCLK_SWAKEUP_FIQ_SOURCE_SHIFT) |
729 (src << SCLK_SWAKEUP_IRQ_SOURCE_SHIFT) |
730 (src << SCLK_SWAKEUP_RUN_SOURCE_SHIFT) |
731 (src << SCLK_SWAKEUP_IDLE_SOURCE_SHIFT) |
732 (SCLK_SYS_STATE_RUN << SCLK_SYS_STATE_SHIFT);
733 writel(val, &clkrst->crc_sclk_brst_pol);
738 * This function is useful on Tegra30, and any later SoCs that have compatible
739 * PLLP configuration registers.
740 * NOTE: Not used on Tegra210 - see tegra210_setup_pllp in T210 clock.c
742 void tegra30_set_up_pllp(void)
744 struct clk_rst_ctlr *clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
748 * Based on the Tegra TRM, the system clock (which is the AVP clock) can
749 * run up to 275MHz. On power on, the default sytem clock source is set
750 * to PLLP_OUT0. This function sets PLLP's (hence PLLP_OUT0's) rate to
751 * 408MHz which is beyond system clock's upper limit.
753 * The fix is to set the system clock to CLK_M before initializing PLLP,
754 * and then switch back to PLLP_OUT4, which has an appropriate divider
755 * configured, after PLLP has been configured
757 set_avp_clock_source(SCLK_SOURCE_CLKM);
760 * PLLP output frequency set to 408Mhz
761 * PLLC output frequency set to 228Mhz
763 switch (clock_get_osc_freq()) {
764 case CLOCK_OSC_FREQ_12_0: /* OSC is 12Mhz */
765 clock_set_rate(CLOCK_ID_PERIPH, 408, 12, 0, 8);
766 clock_set_rate(CLOCK_ID_CGENERAL, 456, 12, 1, 8);
769 case CLOCK_OSC_FREQ_26_0: /* OSC is 26Mhz */
770 clock_set_rate(CLOCK_ID_PERIPH, 408, 26, 0, 8);
771 clock_set_rate(CLOCK_ID_CGENERAL, 600, 26, 0, 8);
774 case CLOCK_OSC_FREQ_13_0: /* OSC is 13Mhz */
775 clock_set_rate(CLOCK_ID_PERIPH, 408, 13, 0, 8);
776 clock_set_rate(CLOCK_ID_CGENERAL, 600, 13, 0, 8);
778 case CLOCK_OSC_FREQ_19_2:
781 * These are not supported. It is too early to print a
782 * message and the UART likely won't work anyway due to the
783 * oscillator being wrong.
788 /* Set PLLP_OUT1, 2, 3 & 4 freqs to 9.6, 48, 102 & 204MHz */
791 /* Assert RSTN before enable */
792 reg = PLLP_OUT2_RSTN_EN | PLLP_OUT1_RSTN_EN;
793 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
794 /* Set divisor and reenable */
795 reg = (IN_408_OUT_48_DIVISOR << PLLP_OUT2_RATIO)
796 | PLLP_OUT2_OVR | PLLP_OUT2_CLKEN | PLLP_OUT2_RSTN_DIS
797 | (IN_408_OUT_9_6_DIVISOR << PLLP_OUT1_RATIO)
798 | PLLP_OUT1_OVR | PLLP_OUT1_CLKEN | PLLP_OUT1_RSTN_DIS;
799 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[0]);
802 /* Assert RSTN before enable */
803 reg = PLLP_OUT4_RSTN_EN | PLLP_OUT3_RSTN_EN;
804 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
805 /* Set divisor and reenable */
806 reg = (IN_408_OUT_204_DIVISOR << PLLP_OUT4_RATIO)
807 | PLLP_OUT4_OVR | PLLP_OUT4_CLKEN | PLLP_OUT4_RSTN_DIS
808 | (IN_408_OUT_102_DIVISOR << PLLP_OUT3_RATIO)
809 | PLLP_OUT3_OVR | PLLP_OUT3_CLKEN | PLLP_OUT3_RSTN_DIS;
810 writel(reg, &clkrst->crc_pll[CLOCK_ID_PERIPH].pll_out[1]);
812 set_avp_clock_source(SCLK_SOURCE_PLLP_OUT4);
815 int clock_external_output(int clk_id)
817 struct pmc_ctlr *pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
819 if (clk_id >= 1 && clk_id <= 3) {
820 setbits_le32(&pmc->pmc_clk_out_cntrl,
821 1 << (2 + (clk_id - 1) * 8));
823 printf("%s: Unknown output clock id %d\n", __func__, clk_id);
830 __weak bool clock_early_init_done(void)