1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (c) 2016-2018, NVIDIA CORPORATION.
7 #include <fdt_support.h>
11 #include <linux/sizes.h>
13 #include <asm/arch/tegra.h>
14 #include <asm/arch-tegra/cboot.h>
15 #include <asm/armv8/mmu.h>
18 * Size of a region that's large enough to hold the relocated U-Boot and all
19 * other allocations made around it (stack, heap, page tables, etc.)
20 * In practice, running "bdinfo" at the shell prompt, the stack reaches about
21 * 5MB from the address selected for ram_top as of the time of writing,
22 * so a 16MB region should be plenty.
24 #define MIN_USABLE_RAM_SIZE SZ_16M
26 * The amount of space we expect to require for stack usage. Used to validate
27 * that all reservations fit into the region selected for the relocation target
29 #define MIN_USABLE_STACK_SIZE SZ_1M
31 DECLARE_GLOBAL_DATA_PTR;
33 extern struct mm_region tegra_mem_map[];
36 * These variables are written to before relocation, and hence cannot be
37 * in.bss, since .bss overlaps the DTB that's appended to the U-Boot binary.
38 * The section attribute forces this into .data and avoids this issue. This
39 * also has the nice side-effect of the content being valid after relocation.
42 /* The number of valid entries in ram_banks[] */
43 static int ram_bank_count __attribute__((section(".data")));
46 * The usable top-of-RAM for U-Boot. This is both:
47 * a) Below 4GB to avoid issues with peripherals that use 32-bit addressing.
48 * b) At the end of a region that has enough space to hold the relocated U-Boot
49 * and all other allocations made around it (stack, heap, page tables, etc.)
51 static u64 ram_top __attribute__((section(".data")));
52 /* The base address of the region of RAM that ends at ram_top */
53 static u64 region_base __attribute__((section(".data")));
55 int cboot_dram_init(void)
58 const void *cboot_blob = (void *)cboot_boot_x0;
65 na = fdtdec_get_uint(cboot_blob, 0, "#address-cells", 2);
66 ns = fdtdec_get_uint(cboot_blob, 0, "#size-cells", 2);
68 node = fdt_path_offset(cboot_blob, "/memory");
70 pr_err("Can't find /memory node in cboot DTB");
73 prop = fdt_getprop(cboot_blob, node, "reg", &len);
75 pr_err("Can't find /memory/reg property in cboot DTB");
79 /* Calculate the true # of base/size pairs to read */
80 len /= 4; /* Convert bytes to number of cells */
81 len /= (na + ns); /* Convert cells to number of banks */
82 if (len > CONFIG_NR_DRAM_BANKS)
83 len = CONFIG_NR_DRAM_BANKS;
85 /* Parse the /memory node, and save useful entries */
88 for (i = 0; i < len; i++) {
89 u64 bank_start, bank_end, bank_size, usable_bank_size;
91 /* Extract raw memory region data from DTB */
92 bank_start = fdt_read_number(prop, na);
94 bank_size = fdt_read_number(prop, ns);
96 gd->ram_size += bank_size;
97 bank_end = bank_start + bank_size;
98 debug("Bank %d: %llx..%llx (+%llx)\n", i,
99 bank_start, bank_end, bank_size);
102 * Align the bank to MMU section size. This is not strictly
103 * necessary, since the translation table construction code
104 * handles page granularity without issue. However, aligning
105 * the MMU entries reduces the size and number of levels in the
106 * page table, so is worth it.
108 bank_start = ROUND(bank_start, SZ_2M);
109 bank_end = bank_end & ~(SZ_2M - 1);
110 bank_size = bank_end - bank_start;
111 debug(" aligned: %llx..%llx (+%llx)\n",
112 bank_start, bank_end, bank_size);
113 if (bank_end <= bank_start)
116 /* Record data used to create MMU translation tables */
118 /* Index below is deliberately 1-based to skip MMIO entry */
119 tegra_mem_map[ram_bank_count].virt = bank_start;
120 tegra_mem_map[ram_bank_count].phys = bank_start;
121 tegra_mem_map[ram_bank_count].size = bank_size;
122 tegra_mem_map[ram_bank_count].attrs =
123 PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_INNER_SHARE;
125 /* Determine best bank to relocate U-Boot into */
126 if (bank_end > SZ_4G)
128 debug(" end %llx (usable)\n", bank_end);
129 usable_bank_size = bank_end - bank_start;
130 debug(" size %llx (usable)\n", usable_bank_size);
131 if ((usable_bank_size >= MIN_USABLE_RAM_SIZE) &&
132 (bank_end > ram_top)) {
134 region_base = bank_start;
135 debug("ram top now %llx\n", ram_top);
139 /* Ensure memory map contains the desired sentinel entry */
140 tegra_mem_map[ram_bank_count + 1].virt = 0;
141 tegra_mem_map[ram_bank_count + 1].phys = 0;
142 tegra_mem_map[ram_bank_count + 1].size = 0;
143 tegra_mem_map[ram_bank_count + 1].attrs = 0;
145 /* Error out if a relocation target couldn't be found */
147 pr_err("Can't find a usable RAM top");
154 int cboot_dram_init_banksize(void)
158 if (ram_bank_count == 0)
161 if ((gd->start_addr_sp - region_base) < MIN_USABLE_STACK_SIZE) {
162 pr_err("Reservations exceed chosen region size");
166 for (i = 0; i < ram_bank_count; i++) {
167 gd->bd->bi_dram[i].start = tegra_mem_map[1 + i].virt;
168 gd->bd->bi_dram[i].size = tegra_mem_map[1 + i].size;
172 gd->pci_ram_top = ram_top;
178 ulong cboot_get_usable_ram_top(ulong total_size)
184 * The following few functions run late during the boot process and dynamically
185 * calculate the load address of various binaries. To keep track of multiple
186 * allocations, some writable list of RAM banks must be used. tegra_mem_map[]
187 * is used for this purpose to avoid making yet another copy of the list of RAM
188 * banks. This is safe because tegra_mem_map[] is only used once during very
189 * early boot to create U-Boot's page tables, long before this code runs. If
190 * this assumption becomes invalid later, we can just fix the code to copy the
191 * list of RAM banks into some private data structure before running.
194 static char *gen_varname(const char *var, const char *ext)
196 size_t len_var = strlen(var);
197 size_t len_ext = strlen(ext);
198 size_t len = len_var + len_ext + 1;
199 char *varext = malloc(len);
204 strcpy(varext + len_var, ext);
208 static void mark_ram_allocated(int bank, u64 allocated_start, u64 allocated_end)
210 u64 bank_start = tegra_mem_map[bank].virt;
211 u64 bank_size = tegra_mem_map[bank].size;
212 u64 bank_end = bank_start + bank_size;
213 bool keep_front = allocated_start != bank_start;
214 bool keep_tail = allocated_end != bank_end;
216 if (keep_front && keep_tail) {
218 * There are CONFIG_NR_DRAM_BANKS DRAM entries in the array,
219 * starting at index 1 (index 0 is MMIO). So, we are at DRAM
220 * entry "bank" not "bank - 1" as for a typical 0-base array.
221 * The number of remaining DRAM entries is therefore
222 * "CONFIG_NR_DRAM_BANKS - bank". We want to duplicate the
223 * current entry and shift up the remaining entries, dropping
224 * the last one. Thus, we must copy one fewer entry than the
227 memmove(&tegra_mem_map[bank + 1], &tegra_mem_map[bank],
228 CONFIG_NR_DRAM_BANKS - bank - 1);
229 tegra_mem_map[bank].size = allocated_start - bank_start;
231 tegra_mem_map[bank].virt = allocated_end;
232 tegra_mem_map[bank].phys = allocated_end;
233 tegra_mem_map[bank].size = bank_end - allocated_end;
234 } else if (keep_front) {
235 tegra_mem_map[bank].size = allocated_start - bank_start;
236 } else if (keep_tail) {
237 tegra_mem_map[bank].virt = allocated_end;
238 tegra_mem_map[bank].phys = allocated_end;
239 tegra_mem_map[bank].size = bank_end - allocated_end;
242 * We could move all subsequent banks down in the array but
243 * that's not necessary for subsequent allocations to work, so
246 tegra_mem_map[bank].size = 0;
250 static void reserve_ram(u64 start, u64 size)
253 u64 end = start + size;
255 for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) {
256 u64 bank_start = tegra_mem_map[bank].virt;
257 u64 bank_size = tegra_mem_map[bank].size;
258 u64 bank_end = bank_start + bank_size;
260 if (end <= bank_start || start > bank_end)
262 mark_ram_allocated(bank, start, end);
267 static u64 alloc_ram(u64 size, u64 align, u64 offset)
271 for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) {
272 u64 bank_start = tegra_mem_map[bank].virt;
273 u64 bank_size = tegra_mem_map[bank].size;
274 u64 bank_end = bank_start + bank_size;
275 u64 allocated = ROUND(bank_start, align) + offset;
276 u64 allocated_end = allocated + size;
278 if (allocated_end > bank_end)
280 mark_ram_allocated(bank, allocated, allocated_end);
286 static void set_calculated_aliases(char *aliases, u64 address)
291 aliases = strdup(aliases);
293 pr_err("strdup(aliases) failed");
299 alias = strsep(&tmp, " ");
302 debug("%s: alias: %s\n", __func__, alias);
303 err = env_set_hex(alias, address);
305 pr_err("Could not set %s\n", alias);
311 static void set_calculated_env_var(const char *var)
324 var_size = gen_varname(var, "_size");
327 var_align = gen_varname(var, "_align");
329 goto out_free_var_size;
330 var_offset = gen_varname(var, "_offset");
332 goto out_free_var_align;
333 var_aliases = gen_varname(var, "_aliases");
335 goto out_free_var_offset;
337 size = env_get_hex(var_size, 0);
339 pr_err("%s not set or zero\n", var_size);
340 goto out_free_var_aliases;
342 align = env_get_hex(var_align, 1);
343 /* Handle extant variables, but with a value of 0 */
346 offset = env_get_hex(var_offset, 0);
347 aliases = env_get(var_aliases);
349 debug("%s: Calc var %s; size=%llx, align=%llx, offset=%llx\n",
350 __func__, var, size, align, offset);
352 debug("%s: Aliases: %s\n", __func__, aliases);
354 address = alloc_ram(size, align, offset);
356 pr_err("Could not allocate %s\n", var);
357 goto out_free_var_aliases;
359 debug("%s: Address %llx\n", __func__, address);
361 err = env_set_hex(var, address);
363 pr_err("Could not set %s\n", var);
365 set_calculated_aliases(aliases, address);
367 out_free_var_aliases:
378 static void dump_ram_banks(void)
382 for (bank = 1; bank <= CONFIG_NR_DRAM_BANKS; bank++) {
383 u64 bank_start = tegra_mem_map[bank].virt;
384 u64 bank_size = tegra_mem_map[bank].size;
385 u64 bank_end = bank_start + bank_size;
389 printf("%d: %010llx..%010llx (+%010llx)\n", bank - 1,
390 bank_start, bank_end, bank_size);
395 static void set_calculated_env_vars(void)
397 char *vars, *tmp, *var;
400 printf("RAM banks before any calculated env. var.s:\n");
404 reserve_ram(cboot_boot_x0, fdt_totalsize(cboot_boot_x0));
407 printf("RAM after reserving cboot DTB:\n");
411 vars = env_get("calculated_vars");
413 debug("%s: No env var calculated_vars\n", __func__);
419 pr_err("strdup(calculated_vars) failed");
425 var = strsep(&tmp, " ");
428 debug("%s: var: %s\n", __func__, var);
429 set_calculated_env_var(var);
431 printf("RAM banks after allocating %s:\n", var);
439 static int set_fdt_addr(void)
443 ret = env_set_hex("fdt_addr", cboot_boot_x0);
445 printf("Failed to set fdt_addr to point at DTB: %d\n", ret);
453 * Attempt to use /chosen/nvidia,ether-mac in the cboot DTB to U-Boot's
454 * ethaddr environment variable if possible.
456 static int set_ethaddr_from_cboot(void)
458 const void *cboot_blob = (void *)cboot_boot_x0;
462 /* Already a valid address in the environment? If so, keep it */
463 if (env_get("ethaddr"))
466 node = fdt_path_offset(cboot_blob, "/chosen");
468 printf("Can't find /chosen node in cboot DTB\n");
471 prop = fdt_getprop(cboot_blob, node, "nvidia,ether-mac", &len);
473 printf("Can't find nvidia,ether-mac property in cboot DTB\n");
477 ret = env_set("ethaddr", (void *)prop);
479 printf("Failed to set ethaddr from cboot DTB: %d\n", ret);
486 int cboot_late_init(void)
488 set_calculated_env_vars();
490 * Ignore errors here; the value may not be used depending on
491 * extlinux.conf or boot script content.
494 /* Ignore errors here; not all cases care about Ethernet addresses */
495 set_ethaddr_from_cboot();