1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (c) 2013-2014, NVIDIA CORPORATION. All rights reserved.
6 /* Tegra cache routines */
10 #include <asm/arch-tegra/ap.h>
11 #if IS_ENABLED(CONFIG_TEGRA_GP_PADCTRL)
12 #include <asm/arch/gp_padctrl.h>
16 void config_cache(void)
20 /* enable SMP mode and FW for CPU0, by writing to Auxiliary Ctl reg */
22 "mrc p15, 0, r0, c1, c0, 1\n"
24 "mcr p15, 0, r0, c1, c0, 1\n");
26 /* Currently, only Tegra114+ needs this L2 cache change to boot Linux */
27 if (tegra_get_chip() < CHIPID_TEGRA114)
31 * Systems with an architectural L2 cache must not use the PL310.
32 * Config L2CTLR here for a data RAM latency of 3 cycles.
34 asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg));
37 asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg));