2 * (C) Copyright 2010,2011
3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
12 #include <linux/compiler.h>
14 #include <asm/arch/clock.h>
16 #include <asm/arch/display.h>
18 #include <asm/arch/funcmux.h>
19 #include <asm/arch/pinmux.h>
20 #include <asm/arch/pmu.h>
21 #ifdef CONFIG_PWM_TEGRA
22 #include <asm/arch/pwm.h>
24 #include <asm/arch/tegra.h>
25 #include <asm/arch-tegra/ap.h>
26 #include <asm/arch-tegra/board.h>
27 #include <asm/arch-tegra/clk_rst.h>
28 #include <asm/arch-tegra/pmc.h>
29 #include <asm/arch-tegra/sys_proto.h>
30 #include <asm/arch-tegra/uart.h>
31 #include <asm/arch-tegra/warmboot.h>
32 #ifdef CONFIG_TEGRA_CLOCK_SCALING
33 #include <asm/arch/emc.h>
35 #ifdef CONFIG_USB_EHCI_TEGRA
36 #include <asm/arch-tegra/usb.h>
39 #ifdef CONFIG_TEGRA_MMC
40 #include <asm/arch-tegra/tegra_mmc.h>
41 #include <asm/arch-tegra/mmc.h>
43 #include <asm/arch-tegra/xusb-padctl.h>
44 #include <power/as3722.h>
49 DECLARE_GLOBAL_DATA_PTR;
51 #ifdef CONFIG_SPL_BUILD
52 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
53 U_BOOT_DEVICE(tegra_gpios) = {
58 __weak void pinmux_init(void) {}
59 __weak void pin_mux_usb(void) {}
60 __weak void pin_mux_spi(void) {}
61 __weak void gpio_early_init_uart(void) {}
62 __weak void pin_mux_display(void) {}
64 #if defined(CONFIG_TEGRA_NAND)
65 __weak void pin_mux_nand(void)
67 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
72 * Routine: power_det_init
73 * Description: turn off power detects
75 static void power_det_init(void)
77 #if defined(CONFIG_TEGRA20)
78 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
80 /* turn off power detects */
81 writel(0, &pmc->pmc_pwr_det_latch);
82 writel(0, &pmc->pmc_pwr_det);
86 __weak int tegra_board_id(void)
91 #ifdef CONFIG_DISPLAY_BOARDINFO
94 int board_id = tegra_board_id();
96 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
98 printf(", ID: %d\n", board_id);
103 #endif /* CONFIG_DISPLAY_BOARDINFO */
105 __weak int tegra_lcd_pmic_init(int board_it)
110 __weak int nvidia_board_init(void)
116 * Routine: board_init
117 * Description: Early hardware init.
121 __maybe_unused int err;
122 __maybe_unused int board_id;
124 /* Do clocks and UART first so that printf() works */
128 #ifdef CONFIG_TEGRA_SPI
132 #ifdef CONFIG_PWM_TEGRA
133 if (pwm_init(gd->fdt_blob))
134 debug("%s: Failed to init pwm\n", __func__);
138 tegra_lcd_check_next_stage(gd->fdt_blob, 0);
140 /* boot param addr */
141 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
145 #ifdef CONFIG_SYS_I2C_TEGRA
146 # ifdef CONFIG_TEGRA_PMU
147 if (pmu_set_nominal())
148 debug("Failed to select nominal voltages\n");
149 # ifdef CONFIG_TEGRA_CLOCK_SCALING
150 err = board_emc_init();
152 debug("Memory controller init failed: %d\n", err);
154 # endif /* CONFIG_TEGRA_PMU */
155 #ifdef CONFIG_AS3722_POWER
156 err = as3722_init(NULL);
157 if (err && err != -ENODEV)
160 #endif /* CONFIG_SYS_I2C_TEGRA */
162 #ifdef CONFIG_USB_EHCI_TEGRA
167 board_id = tegra_board_id();
168 err = tegra_lcd_pmic_init(board_id);
171 tegra_lcd_check_next_stage(gd->fdt_blob, 0);
174 #ifdef CONFIG_TEGRA_NAND
178 tegra_xusb_padctl_init(gd->fdt_blob);
180 #ifdef CONFIG_TEGRA_LP0
181 /* save Sdram params to PMC 2, 4, and 24 for WB0 */
182 warmboot_save_sdram_params();
184 /* prepare the WB code to LP0 location */
185 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
187 return nvidia_board_init();
190 #ifdef CONFIG_BOARD_EARLY_INIT_F
191 static void __gpio_early_init(void)
195 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
197 int board_early_init_f(void)
199 /* Do any special system timer/TSC setup */
200 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
201 if (!tegra_cpu_is_non_secure())
208 /* Initialize periph GPIOs */
210 gpio_early_init_uart();
212 tegra_lcd_early_init(gd->fdt_blob);
217 #endif /* EARLY_INIT */
219 int board_late_init(void)
222 /* Make sure we finish initing the LCD */
223 tegra_lcd_check_next_stage(gd->fdt_blob, 1);
225 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
226 if (tegra_cpu_is_non_secure()) {
227 printf("CPU is in NS mode\n");
228 setenv("cpu_ns_mode", "1");
230 setenv("cpu_ns_mode", "");
236 #if defined(CONFIG_TEGRA_MMC)
237 __weak void pin_mux_mmc(void)
241 /* this is a weak define that we are overriding */
242 int board_mmc_init(bd_t *bd)
244 debug("%s called\n", __func__);
246 /* Enable muxes, etc. for SDMMC controllers */
249 debug("%s: init MMC\n", __func__);
255 void pad_init_mmc(struct mmc_host *host)
257 #if defined(CONFIG_TEGRA30)
258 enum periph_id id = host->mmc_id;
261 debug("%s: sdmmc address = %08x, id = %d\n", __func__,
262 (unsigned int)host->reg, id);
264 /* Set the pad drive strength for SDMMC1 or 3 only */
265 if (id != PERIPH_ID_SDMMC1 && id != PERIPH_ID_SDMMC3) {
266 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
271 val = readl(&host->reg->sdmemcmppadctl);
273 val |= MEMCOMP_PADCTRL_VREF;
274 writel(val, &host->reg->sdmemcmppadctl);
276 val = readl(&host->reg->autocalcfg);
278 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
279 writel(val, &host->reg->autocalcfg);
286 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower
287 * 32-bits of the physical address space. Cap the maximum usable RAM area
288 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
289 * boundary that most devices can address.
291 ulong board_get_usable_ram_top(ulong total_size)
293 if (gd->ram_top > 0x100000000)