1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2010,2011
4 * NVIDIA Corporation <www.nvidia.com>
14 #include <asm/arch-tegra/ap.h>
15 #include <asm/arch-tegra/board.h>
16 #include <asm/arch-tegra/cboot.h>
17 #include <asm/arch-tegra/clk_rst.h>
18 #include <asm/arch-tegra/pmc.h>
19 #include <asm/arch-tegra/pmu.h>
20 #include <asm/arch-tegra/sys_proto.h>
21 #include <asm/arch-tegra/uart.h>
22 #include <asm/arch-tegra/warmboot.h>
23 #include <asm/arch-tegra/gpu.h>
24 #include <asm/arch-tegra/usb.h>
25 #include <asm/arch-tegra/xusb-padctl.h>
26 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
27 #include <asm/arch/clock.h>
29 #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
30 #include <asm/arch/funcmux.h>
31 #include <asm/arch/pinmux.h>
33 #include <asm/arch/tegra.h>
34 #ifdef CONFIG_TEGRA_CLOCK_SCALING
35 #include <asm/arch/emc.h>
39 DECLARE_GLOBAL_DATA_PTR;
41 #ifdef CONFIG_SPL_BUILD
42 /* TODO(sjg@chromium.org): Remove once SPL supports device tree */
43 U_BOOT_DEVICE(tegra_gpios) = {
48 __weak void pinmux_init(void) {}
49 __weak void pin_mux_usb(void) {}
50 __weak void pin_mux_spi(void) {}
51 __weak void pin_mux_mmc(void) {}
52 __weak void gpio_early_init_uart(void) {}
53 __weak void pin_mux_display(void) {}
54 __weak void start_cpu_fan(void) {}
55 __weak void cboot_late_init(void) {}
57 #if defined(CONFIG_TEGRA_NAND)
58 __weak void pin_mux_nand(void)
60 funcmux_select(PERIPH_ID_NDFLASH, FUNCMUX_DEFAULT);
65 * Routine: power_det_init
66 * Description: turn off power detects
68 static void power_det_init(void)
70 #if defined(CONFIG_TEGRA20)
71 struct pmc_ctlr *const pmc = (struct pmc_ctlr *)NV_PA_PMC_BASE;
73 /* turn off power detects */
74 writel(0, &pmc->pmc_pwr_det_latch);
75 writel(0, &pmc->pmc_pwr_det);
79 __weak int tegra_board_id(void)
84 #ifdef CONFIG_DISPLAY_BOARDINFO
87 int board_id = tegra_board_id();
89 printf("Board: %s", CONFIG_TEGRA_BOARD_STRING);
91 printf(", ID: %d\n", board_id);
96 #endif /* CONFIG_DISPLAY_BOARDINFO */
98 __weak int tegra_lcd_pmic_init(int board_it)
103 __weak int nvidia_board_init(void)
109 * Routine: board_init
110 * Description: Early hardware init.
114 __maybe_unused int err;
115 __maybe_unused int board_id;
117 /* Do clocks and UART first so that printf() works */
118 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
125 #ifdef CONFIG_TEGRA_SPI
129 #ifdef CONFIG_MMC_SDHCI_TEGRA
133 /* Init is handled automatically in the driver-model case */
134 #if defined(CONFIG_DM_VIDEO)
137 /* boot param addr */
138 gd->bd->bi_boot_params = (NV_PA_SDRAM_BASE + 0x100);
142 #ifdef CONFIG_SYS_I2C_TEGRA
143 # ifdef CONFIG_TEGRA_PMU
144 if (pmu_set_nominal())
145 debug("Failed to select nominal voltages\n");
146 # ifdef CONFIG_TEGRA_CLOCK_SCALING
147 err = board_emc_init();
149 debug("Memory controller init failed: %d\n", err);
151 # endif /* CONFIG_TEGRA_PMU */
152 #endif /* CONFIG_SYS_I2C_TEGRA */
154 #ifdef CONFIG_USB_EHCI_TEGRA
158 #if defined(CONFIG_DM_VIDEO)
159 board_id = tegra_board_id();
160 err = tegra_lcd_pmic_init(board_id);
162 debug("Failed to set up LCD PMIC\n");
167 #ifdef CONFIG_TEGRA_NAND
171 tegra_xusb_padctl_init();
173 #ifdef CONFIG_TEGRA_LP0
174 /* save Sdram params to PMC 2, 4, and 24 for WB0 */
175 warmboot_save_sdram_params();
177 /* prepare the WB code to LP0 location */
178 warmboot_prepare_code(TEGRA_LP0_ADDR, TEGRA_LP0_SIZE);
180 return nvidia_board_init();
183 #ifdef CONFIG_BOARD_EARLY_INIT_F
184 static void __gpio_early_init(void)
188 void gpio_early_init(void) __attribute__((weak, alias("__gpio_early_init")));
190 int board_early_init_f(void)
192 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
193 if (!clock_early_init_done())
197 #if defined(CONFIG_TEGRA_DISCONNECT_UDC_ON_BOOT)
198 #define USBCMD_FS2 (1 << 15)
200 struct usb_ctlr *usbctlr = (struct usb_ctlr *)0x7d000000;
201 writel(USBCMD_FS2, &usbctlr->usb_cmd);
205 /* Do any special system timer/TSC setup */
206 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
207 # if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
208 if (!tegra_cpu_is_non_secure())
216 /* Initialize periph GPIOs */
218 gpio_early_init_uart();
222 #endif /* EARLY_INIT */
224 int board_late_init(void)
226 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
227 if (tegra_cpu_is_non_secure()) {
228 printf("CPU is in NS mode\n");
229 env_set("cpu_ns_mode", "1");
231 env_set("cpu_ns_mode", "");
241 * In some SW environments, a memory carve-out exists to house a secure
242 * monitor, a trusted OS, and/or various statically allocated media buffers.
244 * This carveout exists at the highest possible address that is within a
245 * 32-bit physical address space.
247 * This function returns the total size of this carve-out. At present, the
248 * returned value is hard-coded for simplicity. In the future, it may be
249 * possible to determine the carve-out size:
250 * - By querying some run-time information source, such as:
251 * - A structure passed to U-Boot by earlier boot software.
253 * - A call into the secure monitor.
254 * - In the per-board U-Boot configuration header, based on knowledge of the
255 * SW environment that U-Boot is being built for.
257 * For now, we support two configurations in U-Boot:
258 * - 32-bit ports without any form of carve-out.
259 * - 64 bit ports which are assumed to use a carve-out of a conservatively
262 static ulong carveout_size(void)
266 #elif defined(CONFIG_ARMV7_SECURE_RESERVE_SIZE)
267 // BASE+SIZE might not == 4GB. If so, we want the carveout to cover
268 // from BASE to 4GB, not BASE to BASE+SIZE.
269 return (0 - CONFIG_ARMV7_SECURE_BASE) & ~(SZ_2M - 1);
276 * Determine the amount of usable RAM below 4GiB, taking into account any
277 * carve-out that may be assigned.
279 static ulong usable_ram_size_below_4g(void)
281 ulong total_size_below_4g;
282 ulong usable_size_below_4g;
285 * The total size of RAM below 4GiB is the lesser address of:
286 * (a) 2GiB itself (RAM starts at 2GiB, and 4GiB - 2GiB == 2GiB).
287 * (b) The size RAM physically present in the system.
289 if (gd->ram_size < SZ_2G)
290 total_size_below_4g = gd->ram_size;
292 total_size_below_4g = SZ_2G;
294 /* Calculate usable RAM by subtracting out any carve-out size */
295 usable_size_below_4g = total_size_below_4g - carveout_size();
297 return usable_size_below_4g;
301 * Represent all available RAM in either one or two banks.
303 * The first bank describes any usable RAM below 4GiB.
304 * The second bank describes any RAM above 4GiB.
306 * This split is driven by the following requirements:
307 * - The NVIDIA L4T kernel requires separate entries in the DT /memory/reg
308 * property for memory below and above the 4GiB boundary. The layout of that
309 * DT property is directly driven by the entries in the U-Boot bank array.
310 * - The potential existence of a carve-out at the end of RAM below 4GiB can
311 * only be represented using multiple banks.
313 * Explicitly removing the carve-out RAM from the bank entries makes the RAM
314 * layout a bit more obvious, e.g. when running "bdinfo" at the U-Boot
317 * This does mean that the DT U-Boot passes to the Linux kernel will not
318 * include this RAM in /memory/reg at all. An alternative would be to include
319 * all RAM in the U-Boot banks (and hence DT), and add a /memreserve/ node
320 * into DT to stop the kernel from using the RAM. IIUC, I don't /think/ the
321 * Linux kernel will ever need to access any RAM in* the carve-out via a CPU
322 * mapping, so either way is acceptable.
324 * On 32-bit systems, we never define a bank for RAM above 4GiB, since the
325 * start address of that bank cannot be represented in the 32-bit .size
328 int dram_init_banksize(void)
332 /* try to compute DRAM bank size based on cboot DTB first */
333 err = cboot_dram_init_banksize();
337 /* fall back to default DRAM bank size computation */
339 gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
340 gd->bd->bi_dram[0].size = usable_ram_size_below_4g();
343 gd->pci_ram_top = gd->bd->bi_dram[0].start + gd->bd->bi_dram[0].size;
346 #ifdef CONFIG_PHYS_64BIT
347 if (gd->ram_size > SZ_2G) {
348 gd->bd->bi_dram[1].start = 0x100000000;
349 gd->bd->bi_dram[1].size = gd->ram_size - SZ_2G;
353 gd->bd->bi_dram[1].start = 0;
354 gd->bd->bi_dram[1].size = 0;
361 * Most hardware on 64-bit Tegra is still restricted to DMA to the lower
362 * 32-bits of the physical address space. Cap the maximum usable RAM area
363 * at 4 GiB to avoid DMA buffers from being allocated beyond the 32-bit
364 * boundary that most devices can address. Also, don't let U-Boot use any
365 * carve-out, as mentioned above.
367 * This function is called before dram_init_banksize(), so we can't simply
368 * return gd->bd->bi_dram[1].start + gd->bd->bi_dram[1].size.
370 ulong board_get_usable_ram_top(ulong total_size)
374 /* try to get top of usable RAM based on cboot DTB first */
375 ram_top = cboot_get_usable_ram_top(total_size);
379 /* fall back to default usable RAM computation */
381 return CONFIG_SYS_SDRAM_BASE + usable_ram_size_below_4g();