1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2010-2015
4 * NVIDIA Corporation <www.nvidia.com>
12 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
13 #include <asm/arch/clock.h>
15 #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
16 #include <asm/arch/funcmux.h>
18 #if IS_ENABLED(CONFIG_TEGRA_MC)
19 #include <asm/arch/mc.h>
21 #include <asm/arch/tegra.h>
22 #include <asm/arch-tegra/ap.h>
23 #include <asm/arch-tegra/board.h>
24 #include <asm/arch-tegra/pmc.h>
25 #include <asm/arch-tegra/sys_proto.h>
26 #include <asm/arch-tegra/warmboot.h>
28 void save_boot_params_ret(void);
30 DECLARE_GLOBAL_DATA_PTR;
33 /* UARTs which we can enable */
42 static bool from_spl __attribute__ ((section(".data")));
44 #ifndef CONFIG_SPL_BUILD
45 void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
48 from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
49 save_boot_params_ret();
53 bool spl_was_boot_source(void)
58 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
59 #if !defined(CONFIG_TEGRA124)
60 #error tegra_cpu_is_non_secure has only been validated on Tegra124
62 bool tegra_cpu_is_non_secure(void)
65 * This register reads 0xffffffff in non-secure mode. This register
66 * only implements bits 31:20, so the lower bits will always read 0 in
67 * secure mode. Thus, the lower bits are an indicator for secure vs.
70 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
71 uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
72 return (mc_s_cfg0 & 1) == 1;
76 #if IS_ENABLED(CONFIG_TEGRA_MC)
77 /* Read the RAM size directly from the memory controller */
78 static phys_size_t query_sdram_size(void)
80 struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
82 phys_size_t size_bytes;
84 emem_cfg = readl(&mc->mc_emem_cfg);
85 #if defined(CONFIG_TEGRA20)
86 debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
87 size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
89 debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
90 #ifndef CONFIG_PHYS_64BIT
92 * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
93 * and will wrap. Clip the reported size to the maximum that a 32-bit
94 * variable can represent (rounded to a page).
96 if (emem_cfg >= 4096) {
97 size_bytes = U32_MAX & ~(0x1000 - 1);
101 /* RAM size EMC is programmed to. */
102 size_bytes = (phys_size_t)emem_cfg * 1024 * 1024;
105 * If all RAM fits within 32-bits, it can be accessed without
106 * LPAE, so go test the RAM size. Otherwise, we can't access
107 * all the RAM, and get_ram_size() would get confused, so
108 * avoid using it. There's no reason we should need this
109 * validation step anyway.
111 if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
112 size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
118 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
119 /* External memory limited to 2047 MB due to IROM/HI-VEC */
120 if (size_bytes == SZ_2G)
130 #if IS_ENABLED(CONFIG_TEGRA_MC)
131 /* We do not initialise DRAM here. We just query the size */
132 gd->ram_size = query_sdram_size();
138 #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
139 static int uart_configs[] = {
140 #if defined(CONFIG_TEGRA20)
141 #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
142 FUNCMUX_UART1_UAA_UAB,
143 #elif defined(CONFIG_TEGRA_UARTA_GPU)
145 #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
148 FUNCMUX_UART1_IRRX_IRTX,
154 #elif defined(CONFIG_TEGRA30)
155 FUNCMUX_UART1_ULPI, /* UARTA */
160 #elif defined(CONFIG_TEGRA114)
164 FUNCMUX_UART4_GMI, /* UARTD */
166 #elif defined(CONFIG_TEGRA124)
167 FUNCMUX_UART1_KBC, /* UARTA */
170 FUNCMUX_UART4_GPIO, /* UARTD */
173 FUNCMUX_UART1_UART1, /* UARTA */
176 FUNCMUX_UART4_UART4, /* UARTD */
182 * Set up the specified uarts
184 * @param uarts_ids Mask containing UARTs to init (UARTx)
186 static void setup_uarts(int uart_ids)
188 static enum periph_id id_for_uart[] = {
197 for (i = 0; i < UART_COUNT; i++) {
198 if (uart_ids & (1 << i)) {
199 enum periph_id id = id_for_uart[i];
201 funcmux_select(id, uart_configs[i]);
202 clock_ll_start_uart(id);
208 void board_init_uart_f(void)
210 #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
211 int uart_ids = 0; /* bit mask of which UART ids to enable */
213 #ifdef CONFIG_TEGRA_ENABLE_UARTA
216 #ifdef CONFIG_TEGRA_ENABLE_UARTB
219 #ifdef CONFIG_TEGRA_ENABLE_UARTC
222 #ifdef CONFIG_TEGRA_ENABLE_UARTD
225 #ifdef CONFIG_TEGRA_ENABLE_UARTE
228 setup_uarts(uart_ids);
232 #if !CONFIG_IS_ENABLED(OF_CONTROL)
233 static struct ns16550_platdata ns16550_com1_pdata = {
234 .base = CONFIG_SYS_NS16550_COM1,
236 .clock = CONFIG_SYS_NS16550_CLK,
237 .fcr = UART_FCR_DEFVAL,
240 U_BOOT_DEVICE(ns16550_com1) = {
241 "ns16550_serial", &ns16550_com1_pdata
245 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
246 void enable_caches(void)
248 /* Enable D-cache. I-cache is already enabled in start.S */