1 // SPDX-License-Identifier: GPL-2.0+
3 * (C) Copyright 2010-2015
4 * NVIDIA Corporation <www.nvidia.com>
14 #include <asm/cache.h>
16 #if IS_ENABLED(CONFIG_TEGRA_CLKRST)
17 #include <asm/arch/clock.h>
19 #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
20 #include <asm/arch/funcmux.h>
22 #if IS_ENABLED(CONFIG_TEGRA_MC)
23 #include <asm/arch/mc.h>
25 #include <asm/arch/tegra.h>
26 #include <asm/arch-tegra/ap.h>
27 #include <asm/arch-tegra/board.h>
28 #include <asm/arch-tegra/cboot.h>
29 #include <asm/arch-tegra/pmc.h>
30 #include <asm/arch-tegra/sys_proto.h>
31 #include <asm/arch-tegra/warmboot.h>
33 void save_boot_params_ret(void);
35 DECLARE_GLOBAL_DATA_PTR;
38 /* UARTs which we can enable */
47 static bool from_spl __attribute__ ((section(".data")));
49 #ifndef CONFIG_SPL_BUILD
50 void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2,
53 from_spl = r0 != UBOOT_NOT_LOADED_FROM_SPL;
56 * The logic for this is somewhat indirect. The purpose of the marker
57 * (UBOOT_NOT_LOADED_FROM_SPL) is in fact used to determine if U-Boot
58 * was loaded from a read-only instance of itself, which is something
59 * that can happen in secure boot setups. So basically the presence
60 * of the marker is an indication that U-Boot was loaded by one such
61 * special variant of U-Boot. Conversely, the absence of the marker
62 * indicates that this instance of U-Boot was loaded by something
63 * other than a special U-Boot. This could be SPL, but it could just
64 * as well be one of any number of other first stage bootloaders.
67 cboot_save_boot_params(r0, r1, r2, r3);
69 save_boot_params_ret();
73 bool spl_was_boot_source(void)
78 #if defined(CONFIG_TEGRA_SUPPORT_NON_SECURE)
79 #if !defined(CONFIG_TEGRA124)
80 #error tegra_cpu_is_non_secure has only been validated on Tegra124
82 bool tegra_cpu_is_non_secure(void)
85 * This register reads 0xffffffff in non-secure mode. This register
86 * only implements bits 31:20, so the lower bits will always read 0 in
87 * secure mode. Thus, the lower bits are an indicator for secure vs.
90 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
91 uint32_t mc_s_cfg0 = readl(&mc->mc_security_cfg0);
92 return (mc_s_cfg0 & 1) == 1;
96 #if IS_ENABLED(CONFIG_TEGRA_MC)
97 /* Read the RAM size directly from the memory controller */
98 static phys_size_t query_sdram_size(void)
100 struct mc_ctlr *const mc = (struct mc_ctlr *)NV_PA_MC_BASE;
102 phys_size_t size_bytes;
104 emem_cfg = readl(&mc->mc_emem_cfg);
105 #if defined(CONFIG_TEGRA20)
106 debug("mc->mc_emem_cfg (MEM_SIZE_KB) = 0x%08x\n", emem_cfg);
107 size_bytes = get_ram_size((void *)PHYS_SDRAM_1, emem_cfg * 1024);
109 debug("mc->mc_emem_cfg (MEM_SIZE_MB) = 0x%08x\n", emem_cfg);
110 #ifndef CONFIG_PHYS_64BIT
112 * If >=4GB RAM is present, the byte RAM size won't fit into 32-bits
113 * and will wrap. Clip the reported size to the maximum that a 32-bit
114 * variable can represent (rounded to a page).
116 if (emem_cfg >= 4096) {
117 size_bytes = U32_MAX & ~(0x1000 - 1);
121 /* RAM size EMC is programmed to. */
122 size_bytes = (phys_size_t)emem_cfg * 1024 * 1024;
125 * If all RAM fits within 32-bits, it can be accessed without
126 * LPAE, so go test the RAM size. Otherwise, we can't access
127 * all the RAM, and get_ram_size() would get confused, so
128 * avoid using it. There's no reason we should need this
129 * validation step anyway.
131 if (emem_cfg <= (0 - PHYS_SDRAM_1) / (1024 * 1024))
132 size_bytes = get_ram_size((void *)PHYS_SDRAM_1,
138 #if defined(CONFIG_TEGRA30) || defined(CONFIG_TEGRA114)
139 /* External memory limited to 2047 MB due to IROM/HI-VEC */
140 if (size_bytes == SZ_2G)
152 /* try to initialize DRAM from cboot DTB first */
153 err = cboot_dram_init();
157 #if IS_ENABLED(CONFIG_TEGRA_MC)
158 /* We do not initialise DRAM here. We just query the size */
159 gd->ram_size = query_sdram_size();
165 #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
166 static int uart_configs[] = {
167 #if defined(CONFIG_TEGRA20)
168 #if defined(CONFIG_TEGRA_UARTA_UAA_UAB)
169 FUNCMUX_UART1_UAA_UAB,
170 #elif defined(CONFIG_TEGRA_UARTA_GPU)
172 #elif defined(CONFIG_TEGRA_UARTA_SDIO1)
175 FUNCMUX_UART1_IRRX_IRTX,
181 #elif defined(CONFIG_TEGRA30)
182 FUNCMUX_UART1_ULPI, /* UARTA */
187 #elif defined(CONFIG_TEGRA114)
191 FUNCMUX_UART4_GMI, /* UARTD */
193 #elif defined(CONFIG_TEGRA124)
194 FUNCMUX_UART1_KBC, /* UARTA */
197 FUNCMUX_UART4_GPIO, /* UARTD */
200 FUNCMUX_UART1_UART1, /* UARTA */
203 FUNCMUX_UART4_UART4, /* UARTD */
209 * Set up the specified uarts
211 * @param uarts_ids Mask containing UARTs to init (UARTx)
213 static void setup_uarts(int uart_ids)
215 static enum periph_id id_for_uart[] = {
224 for (i = 0; i < UART_COUNT; i++) {
225 if (uart_ids & (1 << i)) {
226 enum periph_id id = id_for_uart[i];
228 funcmux_select(id, uart_configs[i]);
229 clock_ll_start_uart(id);
235 void board_init_uart_f(void)
237 #if IS_ENABLED(CONFIG_TEGRA_PINCTRL)
238 int uart_ids = 0; /* bit mask of which UART ids to enable */
240 #ifdef CONFIG_TEGRA_ENABLE_UARTA
243 #ifdef CONFIG_TEGRA_ENABLE_UARTB
246 #ifdef CONFIG_TEGRA_ENABLE_UARTC
249 #ifdef CONFIG_TEGRA_ENABLE_UARTD
252 #ifdef CONFIG_TEGRA_ENABLE_UARTE
255 setup_uarts(uart_ids);
259 #if !CONFIG_IS_ENABLED(OF_CONTROL)
260 static struct ns16550_platdata ns16550_com1_pdata = {
261 .base = CONFIG_SYS_NS16550_COM1,
263 .clock = CONFIG_SYS_NS16550_CLK,
264 .fcr = UART_FCR_DEFVAL,
267 U_BOOT_DEVICE(ns16550_com1) = {
268 "ns16550_serial", &ns16550_com1_pdata
272 #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
273 void enable_caches(void)
275 /* Enable D-cache. I-cache is already enabled in start.S */