4 * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
5 * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
8 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
10 * SPDX-License-Identifier: GPL-2.0+
14 #include <asm/arch/clock.h>
15 #include <asm/arch/cpu.h>
16 #include <asm/arch/usb_phy.h>
21 #if defined(CONFIG_MACH_SUN4I) || \
22 defined(CONFIG_MACH_SUN5I) || \
23 defined(CONFIG_MACH_SUN6I) || \
24 defined(CONFIG_MACH_SUN7I) || \
25 defined(CONFIG_MACH_SUN8I_A23) || \
26 defined(CONFIG_MACH_SUN9I)
27 #define SUNXI_USB_CSR 0x404
29 #define SUNXI_USB_CSR 0x410
32 #define SUNXI_USB_PMU_IRQ_ENABLE 0x800
33 #define SUNXI_USB_PASSBY_EN 1
35 #define SUNXI_EHCI_AHB_ICHR8_EN (1 << 10)
36 #define SUNXI_EHCI_AHB_INCR4_BURST_EN (1 << 9)
37 #define SUNXI_EHCI_AHB_INCRX_ALIGN_EN (1 << 8)
38 #define SUNXI_EHCI_ULPI_BYPASS_EN (1 << 0)
40 #define REG_PHY_UNK_H3 0x420
41 #define REG_PMU_UNK_H3 0x810
43 /* A83T specific control bits for PHY0 */
44 #define SUNXI_PHY_CTL_VBUSVLDEXT BIT(5)
45 #define SUNXI_PHY_CTL_SIDDQ BIT(3)
47 /* A83T HSIC specific bits */
48 #define SUNXI_EHCI_HS_FORCE BIT(20)
49 #define SUNXI_EHCI_CONNECT_DET BIT(17)
50 #define SUNXI_EHCI_CONNECT_INT BIT(16)
51 #define SUNXI_EHCI_HSIC BIT(1)
53 static struct sunxi_usb_phy {
64 .usb_rst_mask = CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK,
66 .base = SUNXI_USB0_BASE,
69 .usb_rst_mask = CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK,
71 .base = SUNXI_USB1_BASE,
73 #if CONFIG_SUNXI_USB_PHYS >= 3
75 #ifdef CONFIG_MACH_SUN8I_A83T
76 .usb_rst_mask = CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |
79 .usb_rst_mask = CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK,
82 .base = SUNXI_USB2_BASE,
85 #if CONFIG_SUNXI_USB_PHYS >= 4
87 .usb_rst_mask = CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK,
89 .base = SUNXI_USB3_BASE,
94 static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
96 static int get_vbus_gpio(int index)
99 case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_PIN);
100 case 1: return sunxi_name_to_gpio(CONFIG_USB1_VBUS_PIN);
101 case 2: return sunxi_name_to_gpio(CONFIG_USB2_VBUS_PIN);
102 case 3: return sunxi_name_to_gpio(CONFIG_USB3_VBUS_PIN);
107 static int get_vbus_detect_gpio(int index)
110 case 0: return sunxi_name_to_gpio(CONFIG_USB0_VBUS_DET);
115 static int get_id_detect_gpio(int index)
118 case 0: return sunxi_name_to_gpio(CONFIG_USB0_ID_DET);
123 __maybe_unused static void usb_phy_write(struct sunxi_usb_phy *phy, int addr,
126 int j = 0, usbc_bit = 0;
127 void *dest = (void *)SUNXI_USB0_BASE + SUNXI_USB_CSR;
129 #ifdef CONFIG_MACH_SUN8I_A33
130 /* CSR needs to be explicitly initialized to 0 on A33 */
134 usbc_bit = 1 << (phy->id * 2);
135 for (j = 0; j < len; j++) {
136 /* set the bit address to be written */
137 clrbits_le32(dest, 0xff << 8);
138 setbits_le32(dest, (addr + j) << 8);
140 clrbits_le32(dest, usbc_bit);
143 setbits_le32(dest, 1 << 7);
145 clrbits_le32(dest, 1 << 7);
147 setbits_le32(dest, usbc_bit);
149 clrbits_le32(dest, usbc_bit);
155 #if defined(CONFIG_MACH_SUNXI_H3_H5) || defined(CONFIG_MACH_SUN50I)
156 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
158 #if defined CONFIG_MACH_SUNXI_H3_H5
160 clrbits_le32(SUNXI_USBPHY_BASE + REG_PHY_UNK_H3, 0x01);
162 clrbits_le32(phy->base + REG_PMU_UNK_H3, 0x02);
164 #elif defined CONFIG_MACH_SUN8I_A83T
165 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
169 static void sunxi_usb_phy_config(struct sunxi_usb_phy *phy)
171 /* The following comments are machine
172 * translated from Chinese, you have been warned!
175 /* Regulation 45 ohms */
177 usb_phy_write(phy, 0x0c, 0x01, 1);
179 /* adjust PHY's magnitude and rate */
180 usb_phy_write(phy, 0x20, 0x14, 5);
182 /* threshold adjustment disconnect */
183 #if defined CONFIG_MACH_SUN5I || defined CONFIG_MACH_SUN7I
184 usb_phy_write(phy, 0x2a, 2, 2);
186 usb_phy_write(phy, 0x2a, 3, 2);
193 static void sunxi_usb_phy_passby(struct sunxi_usb_phy *phy, int enable)
195 unsigned long bits = 0;
198 addr = (void *)phy->base + SUNXI_USB_PMU_IRQ_ENABLE;
200 bits = SUNXI_EHCI_AHB_ICHR8_EN |
201 SUNXI_EHCI_AHB_INCR4_BURST_EN |
202 SUNXI_EHCI_AHB_INCRX_ALIGN_EN |
203 SUNXI_EHCI_ULPI_BYPASS_EN;
205 #ifdef CONFIG_MACH_SUN8I_A83T
207 bits |= SUNXI_EHCI_HS_FORCE |
208 SUNXI_EHCI_CONNECT_INT |
213 setbits_le32(addr, bits);
215 clrbits_le32(addr, bits);
220 void sunxi_usb_phy_enable_squelch_detect(int index, int enable)
222 #ifndef CONFIG_MACH_SUN8I_A83T
223 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
225 usb_phy_write(phy, 0x3c, enable ? 0 : 2, 2);
229 void sunxi_usb_phy_init(int index)
231 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
232 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
235 if (phy->init_count != 1)
238 setbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
240 sunxi_usb_phy_config(phy);
243 sunxi_usb_phy_passby(phy, SUNXI_USB_PASSBY_EN);
245 #ifdef CONFIG_MACH_SUN8I_A83T
247 setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
248 SUNXI_PHY_CTL_VBUSVLDEXT);
249 clrbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
250 SUNXI_PHY_CTL_SIDDQ);
255 void sunxi_usb_phy_exit(int index)
257 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
258 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
261 if (phy->init_count != 0)
265 sunxi_usb_phy_passby(phy, !SUNXI_USB_PASSBY_EN);
267 #ifdef CONFIG_MACH_SUN8I_A83T
269 setbits_le32(SUNXI_USB0_BASE + SUNXI_USB_CSR,
270 SUNXI_PHY_CTL_SIDDQ);
274 clrbits_le32(&ccm->usb_clk_cfg, phy->usb_rst_mask);
277 void sunxi_usb_phy_power_on(int index)
279 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
281 if (initial_usb_scan_delay) {
282 mdelay(initial_usb_scan_delay);
283 initial_usb_scan_delay = 0;
286 phy->power_on_count++;
287 if (phy->power_on_count != 1)
290 if (phy->gpio_vbus >= 0)
291 gpio_set_value(phy->gpio_vbus, 1);
294 void sunxi_usb_phy_power_off(int index)
296 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
298 phy->power_on_count--;
299 if (phy->power_on_count != 0)
302 if (phy->gpio_vbus >= 0)
303 gpio_set_value(phy->gpio_vbus, 0);
306 int sunxi_usb_phy_vbus_detect(int index)
308 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
309 int err, retries = 3;
311 if (phy->gpio_vbus_det < 0)
312 return phy->gpio_vbus_det;
314 err = gpio_get_value(phy->gpio_vbus_det);
316 * Vbus may have been provided by the board and just been turned of
317 * some milliseconds ago on reset, what we're measuring then is a
318 * residual charge on Vbus, sleep a bit and try again.
320 while (err > 0 && retries--) {
322 err = gpio_get_value(phy->gpio_vbus_det);
328 int sunxi_usb_phy_id_detect(int index)
330 struct sunxi_usb_phy *phy = &sunxi_usb_phy[index];
332 if (phy->gpio_id_det < 0)
333 return phy->gpio_id_det;
335 return gpio_get_value(phy->gpio_id_det);
338 int sunxi_usb_phy_probe(void)
340 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
341 struct sunxi_usb_phy *phy;
344 for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
345 phy = &sunxi_usb_phy[i];
347 phy->gpio_vbus = get_vbus_gpio(i);
348 if (phy->gpio_vbus >= 0) {
349 ret = gpio_request(phy->gpio_vbus, "usb_vbus");
352 ret = gpio_direction_output(phy->gpio_vbus, 0);
357 phy->gpio_vbus_det = get_vbus_detect_gpio(i);
358 if (phy->gpio_vbus_det >= 0) {
359 ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
362 ret = gpio_direction_input(phy->gpio_vbus_det);
367 phy->gpio_id_det = get_id_detect_gpio(i);
368 if (phy->gpio_id_det >= 0) {
369 ret = gpio_request(phy->gpio_id_det, "usb_id_det");
372 ret = gpio_direction_input(phy->gpio_id_det);
375 sunxi_gpio_set_pull(phy->gpio_id_det,
380 setbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
385 int sunxi_usb_phy_remove(void)
387 struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
388 struct sunxi_usb_phy *phy;
391 clrbits_le32(&ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
393 for (i = 0; i < CONFIG_SUNXI_USB_PHYS; i++) {
394 phy = &sunxi_usb_phy[i];
396 if (phy->gpio_vbus >= 0)
397 gpio_free(phy->gpio_vbus);
399 if (phy->gpio_vbus_det >= 0)
400 gpio_free(phy->gpio_vbus_det);
402 if (phy->gpio_id_det >= 0)
403 gpio_free(phy->gpio_id_det);