arch/arm/mach-sunxi/spl_spi_sunxi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Siarhei Siamashka <siarhei.siamashka@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <spl.h>
   8 #include <asm/gpio.h>
   9 #include <asm/io.h>
  10 #include <linux/libfdt.h>
  11
  12 #ifdef CONFIG_SPL_OS_BOOT
  13 #error CONFIG_SPL_OS_BOOT is not supported yet
  14 #endif
  15
  16 /*
  17  * This is a very simple U-Boot image loading implementation, trying to
  18  * replicate what the boot ROM is doing when loading the SPL. Because we
  19  * know the exact pins where the SPI Flash is connected and also know
  20  * that the Read Data Bytes (03h) command is supported, the hardware
  21  * configuration is very simple and we don't need the extra flexibility
  22  * of the SPI framework. Moreover, we rely on the default settings of
  23  * the SPI controler hardware registers and only adjust what needs to
  24  * be changed. This is good for the code size and this implementation
  25  * adds less than 400 bytes to the SPL.
  26  *
  27  * There are two variants of the SPI controller in Allwinner SoCs:
  28  * A10/A13/A20 (sun4i variant) and everything else (sun6i variant).
  29  * Both of them are supported.
  30  *
  31  * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are
  32  * supported at the moment.
  33  */
  34
  35 /*****************************************************************************/
  36 /* SUN4I variant of the SPI controller                                       */
  37 /*****************************************************************************/
  38
  39 #define SUN4I_SPI0_CCTL             0x1C
  40 #define SUN4I_SPI0_CTL              0x08
  41 #define SUN4I_SPI0_RX               0x00
  42 #define SUN4I_SPI0_TX               0x04
  43 #define SUN4I_SPI0_FIFO_STA         0x28
  44 #define SUN4I_SPI0_BC               0x20
  45 #define SUN4I_SPI0_TC               0x24
  46
  47 #define SUN4I_CTL_ENABLE            BIT(0)
  48 #define SUN4I_CTL_MASTER            BIT(1)
  49 #define SUN4I_CTL_TF_RST            BIT(8)
  50 #define SUN4I_CTL_RF_RST            BIT(9)
  51 #define SUN4I_CTL_XCH               BIT(10)
  52
  53 /*****************************************************************************/
  54 /* SUN6I variant of the SPI controller                                       */
  55 /*****************************************************************************/
  56
  57 #define SUN6I_SPI0_CCTL             0x24
  58 #define SUN6I_SPI0_GCR              0x04
  59 #define SUN6I_SPI0_TCR              0x08
  60 #define SUN6I_SPI0_FIFO_STA         0x1C
  61 #define SUN6I_SPI0_MBC              0x30
  62 #define SUN6I_SPI0_MTC              0x34
  63 #define SUN6I_SPI0_BCC              0x38
  64 #define SUN6I_SPI0_TXD              0x200
  65 #define SUN6I_SPI0_RXD              0x300
  66
  67 #define SUN6I_CTL_ENABLE            BIT(0)
  68 #define SUN6I_CTL_MASTER            BIT(1)
  69 #define SUN6I_CTL_SRST              BIT(31)
  70 #define SUN6I_TCR_XCH               BIT(31)
  71
  72 /*****************************************************************************/
  73
  74 #define CCM_AHB_GATING0             (0x01C20000 + 0x60)
  75 #define CCM_H6_SPI_BGR_REG          (0x03001000 + 0x96c)
  76 #ifdef CONFIG_MACH_SUN50I_H6
  77 #define CCM_SPI0_CLK                (0x03001000 + 0x940)
  78 #else
  79 #define CCM_SPI0_CLK                (0x01C20000 + 0xA0)
  80 #endif
  81 #define SUN6I_BUS_SOFT_RST_REG0     (0x01C20000 + 0x2C0)
  82
  83 #define AHB_RESET_SPI0_SHIFT        20
  84 #define AHB_GATE_OFFSET_SPI0        20
  85
  86 #define SPI0_CLK_DIV_BY_2           0x1000
  87 #define SPI0_CLK_DIV_BY_4           0x1001
  88
  89 /*****************************************************************************/
  90
  91 /*
  92  * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
  93  * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
  94  * The H6 uses PC0, PC2, PC3, PC5.
  95  */
  96 static void spi0_pinmux_setup(unsigned int pin_function)
  97 {
  98         /* All chips use PC0 and PC2. */
  99         sunxi_gpio_set_cfgpin(SUNXI_GPC(0), pin_function);
 100         sunxi_gpio_set_cfgpin(SUNXI_GPC(2), pin_function);
 101
 102         /* All chips except H6 use PC1, and only H6 uses PC5. */
 103         if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 104                 sunxi_gpio_set_cfgpin(SUNXI_GPC(1), pin_function);
 105         else
 106                 sunxi_gpio_set_cfgpin(SUNXI_GPC(5), pin_function);
 107
 108         /* Older generations use PC23 for CS, newer ones use PC3. */
 109         if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I) ||
 110             IS_ENABLED(CONFIG_MACH_SUN8I_R40))
 111                 sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
 112         else
 113                 sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
 114 }
 115
 116 static bool is_sun6i_gen_spi(void)
 117 {
 118         return IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ||
 119                IS_ENABLED(CONFIG_MACH_SUN50I_H6);
 120 }
 121
 122 static uintptr_t spi0_base_address(void)
 123 {
 124         if (IS_ENABLED(CONFIG_MACH_SUN8I_R40))
 125                 return 0x01C05000;
 126
 127         if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 128                 return 0x05010000;
 129
 130         if (!is_sun6i_gen_spi())
 131                 return 0x01C05000;
 132
 133         return 0x01C68000;
 134 }
 135
 136 /*
 137  * Setup 6 MHz from OSC24M (because the BROM is doing the same).
 138  */
 139 static void spi0_enable_clock(void)
 140 {
 141         uintptr_t base = spi0_base_address();
 142
 143         /* Deassert SPI0 reset on SUN6I */
 144         if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 145                 setbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
 146         else if (is_sun6i_gen_spi())
 147                 setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
 148                              (1 << AHB_RESET_SPI0_SHIFT));
 149
 150         /* Open the SPI0 gate */
 151         if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 152                 setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
 153
 154         /* Divide by 4 */
 155         writel(SPI0_CLK_DIV_BY_4, base + (is_sun6i_gen_spi() ?
 156                                   SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
 157         /* 24MHz from OSC24M */
 158         writel((1 << 31), CCM_SPI0_CLK);
 159
 160         if (is_sun6i_gen_spi()) {
 161                 /* Enable SPI in the master mode and do a soft reset */
 162                 setbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
 163                              SUN6I_CTL_ENABLE | SUN6I_CTL_SRST);
 164                 /* Wait for completion */
 165                 while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST)
 166                         ;
 167         } else {
 168                 /* Enable SPI in the master mode and reset FIFO */
 169                 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
 170                                                     SUN4I_CTL_ENABLE |
 171                                                     SUN4I_CTL_TF_RST |
 172                                                     SUN4I_CTL_RF_RST);
 173         }
 174 }
 175
 176 static void spi0_disable_clock(void)
 177 {
 178         uintptr_t base = spi0_base_address();
 179
 180         /* Disable the SPI0 controller */
 181         if (is_sun6i_gen_spi())
 182                 clrbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
 183                                              SUN6I_CTL_ENABLE);
 184         else
 185                 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
 186                                              SUN4I_CTL_ENABLE);
 187
 188         /* Disable the SPI0 clock */
 189         writel(0, CCM_SPI0_CLK);
 190
 191         /* Close the SPI0 gate */
 192         if (!IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 193                 clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
 194
 195         /* Assert SPI0 reset on SUN6I */
 196         if (IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 197                 clrbits_le32(CCM_H6_SPI_BGR_REG, (1U << 16) | 0x1);
 198         else if (is_sun6i_gen_spi())
 199                 clrbits_le32(SUN6I_BUS_SOFT_RST_REG0,
 200                              (1 << AHB_RESET_SPI0_SHIFT));
 201 }
 202
 203 static void spi0_init(void)
 204 {
 205         unsigned int pin_function = SUNXI_GPC_SPI0;
 206
 207         if (IS_ENABLED(CONFIG_MACH_SUN50I) ||
 208             IS_ENABLED(CONFIG_MACH_SUN50I_H6))
 209                 pin_function = SUN50I_GPC_SPI0;
 210
 211         spi0_pinmux_setup(pin_function);
 212         spi0_enable_clock();
 213 }
 214
 215 static void spi0_deinit(void)
 216 {
 217         /* New SoCs can disable pins, older could only set them as input */
 218         unsigned int pin_function = SUNXI_GPIO_INPUT;
 219
 220         if (is_sun6i_gen_spi())
 221                 pin_function = SUNXI_GPIO_DISABLE;
 222
 223         spi0_disable_clock();
 224         spi0_pinmux_setup(pin_function);
 225 }
 226
 227 /*****************************************************************************/
 228
 229 #define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */
 230
 231 static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize,
 232                                  ulong spi_ctl_reg,
 233                                  ulong spi_ctl_xch_bitmask,
 234                                  ulong spi_fifo_reg,
 235                                  ulong spi_tx_reg,
 236                                  ulong spi_rx_reg,
 237                                  ulong spi_bc_reg,
 238                                  ulong spi_tc_reg,
 239                                  ulong spi_bcc_reg)
 240 {
 241         writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */
 242         writel(4, spi_tc_reg);           /* Transfer counter (bytes to send) */
 243         if (spi_bcc_reg)
 244                 writel(4, spi_bcc_reg);  /* SUN6I also needs this */
 245
 246         /* Send the Read Data Bytes (03h) command header */
 247         writeb(0x03, spi_tx_reg);
 248         writeb((u8)(addr >> 16), spi_tx_reg);
 249         writeb((u8)(addr >> 8), spi_tx_reg);
 250         writeb((u8)(addr), spi_tx_reg);
 251
 252         /* Start the data transfer */
 253         setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask);
 254
 255         /* Wait until everything is received in the RX FIFO */
 256         while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize)
 257                 ;
 258
 259         /* Skip 4 bytes */
 260         readl(spi_rx_reg);
 261
 262         /* Read the data */
 263         while (bufsize-- > 0)
 264                 *buf++ = readb(spi_rx_reg);
 265
 266         /* tSHSL time is up to 100 ns in various SPI flash datasheets */
 267         udelay(1);
 268 }
 269
 270 static void spi0_read_data(void *buf, u32 addr, u32 len)
 271 {
 272         u8 *buf8 = buf;
 273         u32 chunk_len;
 274         uintptr_t base = spi0_base_address();
 275
 276         while (len > 0) {
 277                 chunk_len = len;
 278                 if (chunk_len > SPI_READ_MAX_SIZE)
 279                         chunk_len = SPI_READ_MAX_SIZE;
 280
 281                 if (is_sun6i_gen_spi()) {
 282                         sunxi_spi0_read_data(buf8, addr, chunk_len,
 283                                              base + SUN6I_SPI0_TCR,
 284                                              SUN6I_TCR_XCH,
 285                                              base + SUN6I_SPI0_FIFO_STA,
 286                                              base + SUN6I_SPI0_TXD,
 287                                              base + SUN6I_SPI0_RXD,
 288                                              base + SUN6I_SPI0_MBC,
 289                                              base + SUN6I_SPI0_MTC,
 290                                              base + SUN6I_SPI0_BCC);
 291                 } else {
 292                         sunxi_spi0_read_data(buf8, addr, chunk_len,
 293                                              base + SUN4I_SPI0_CTL,
 294                                              SUN4I_CTL_XCH,
 295                                              base + SUN4I_SPI0_FIFO_STA,
 296                                              base + SUN4I_SPI0_TX,
 297                                              base + SUN4I_SPI0_RX,
 298                                              base + SUN4I_SPI0_BC,
 299                                              base + SUN4I_SPI0_TC,
 300                                              0);
 301                 }
 302
 303                 len  -= chunk_len;
 304                 buf8 += chunk_len;
 305                 addr += chunk_len;
 306         }
 307 }
 308
 309 static ulong spi_load_read(struct spl_load_info *load, ulong sector,
 310                            ulong count, void *buf)
 311 {
 312         spi0_read_data(buf, sector, count);
 313
 314         return count;
 315 }
 316
 317 /*****************************************************************************/
 318
 319 static int spl_spi_load_image(struct spl_image_info *spl_image,
 320                               struct spl_boot_device *bootdev)
 321 {
 322         int ret = 0;
 323         struct image_header *header;
 324         header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
 325
 326         spi0_init();
 327
 328         spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40);
 329
 330         if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
 331                 image_get_magic(header) == FDT_MAGIC) {
 332                 struct spl_load_info load;
 333
 334                 debug("Found FIT image\n");
 335                 load.dev = NULL;
 336                 load.priv = NULL;
 337                 load.filename = NULL;
 338                 load.bl_len = 1;
 339                 load.read = spi_load_read;
 340                 ret = spl_load_simple_fit(spl_image, &load,
 341                                           CONFIG_SYS_SPI_U_BOOT_OFFS, header);
 342         } else {
 343                 ret = spl_parse_image_header(spl_image, header);
 344                 if (ret)
 345                         return ret;
 346
 347                 spi0_read_data((void *)spl_image->load_addr,
 348                                CONFIG_SYS_SPI_U_BOOT_OFFS, spl_image->size);
 349         }
 350
 351         spi0_deinit();
 352
 353         return ret;
 354 }
 355 /* Use priorty 0 to override the default if it happens to be linked in */
 356 SPL_LOAD_IMAGE_METHOD("sunxi SPI", 0, BOOT_DEVICE_SPI, spl_spi_load_image);