arch/arm/mach-sunxi/spl_spi_sunxi.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright (C) 2016 Siarhei Siamashka <siarhei.siamashka@gmail.com>
   4  */
   5
   6 #include <common.h>
   7 #include <spl.h>
   8 #include <asm/gpio.h>
   9 #include <asm/io.h>
  10 #include <linux/libfdt.h>
  11
  12 #ifdef CONFIG_SPL_OS_BOOT
  13 #error CONFIG_SPL_OS_BOOT is not supported yet
  14 #endif
  15
  16 /*
  17  * This is a very simple U-Boot image loading implementation, trying to
  18  * replicate what the boot ROM is doing when loading the SPL. Because we
  19  * know the exact pins where the SPI Flash is connected and also know
  20  * that the Read Data Bytes (03h) command is supported, the hardware
  21  * configuration is very simple and we don't need the extra flexibility
  22  * of the SPI framework. Moreover, we rely on the default settings of
  23  * the SPI controler hardware registers and only adjust what needs to
  24  * be changed. This is good for the code size and this implementation
  25  * adds less than 400 bytes to the SPL.
  26  *
  27  * There are two variants of the SPI controller in Allwinner SoCs:
  28  * A10/A13/A20 (sun4i variant) and everything else (sun6i variant).
  29  * Both of them are supported.
  30  *
  31  * The pin mixing part is SoC specific and only A10/A13/A20/H3/A64 are
  32  * supported at the moment.
  33  */
  34
  35 /*****************************************************************************/
  36 /* SUN4I variant of the SPI controller                                       */
  37 /*****************************************************************************/
  38
  39 #define SUN4I_SPI0_CCTL             0x1C
  40 #define SUN4I_SPI0_CTL              0x08
  41 #define SUN4I_SPI0_RX               0x00
  42 #define SUN4I_SPI0_TX               0x04
  43 #define SUN4I_SPI0_FIFO_STA         0x28
  44 #define SUN4I_SPI0_BC               0x20
  45 #define SUN4I_SPI0_TC               0x24
  46
  47 #define SUN4I_CTL_ENABLE            BIT(0)
  48 #define SUN4I_CTL_MASTER            BIT(1)
  49 #define SUN4I_CTL_TF_RST            BIT(8)
  50 #define SUN4I_CTL_RF_RST            BIT(9)
  51 #define SUN4I_CTL_XCH               BIT(10)
  52
  53 /*****************************************************************************/
  54 /* SUN6I variant of the SPI controller                                       */
  55 /*****************************************************************************/
  56
  57 #define SUN6I_SPI0_CCTL             0x24
  58 #define SUN6I_SPI0_GCR              0x04
  59 #define SUN6I_SPI0_TCR              0x08
  60 #define SUN6I_SPI0_FIFO_STA         0x1C
  61 #define SUN6I_SPI0_MBC              0x30
  62 #define SUN6I_SPI0_MTC              0x34
  63 #define SUN6I_SPI0_BCC              0x38
  64 #define SUN6I_SPI0_TXD              0x200
  65 #define SUN6I_SPI0_RXD              0x300
  66
  67 #define SUN6I_CTL_ENABLE            BIT(0)
  68 #define SUN6I_CTL_MASTER            BIT(1)
  69 #define SUN6I_CTL_SRST              BIT(31)
  70 #define SUN6I_TCR_XCH               BIT(31)
  71
  72 /*****************************************************************************/
  73
  74 #define CCM_AHB_GATING0             (0x01C20000 + 0x60)
  75 #define CCM_SPI0_CLK                (0x01C20000 + 0xA0)
  76 #define SUN6I_BUS_SOFT_RST_REG0     (0x01C20000 + 0x2C0)
  77
  78 #define AHB_RESET_SPI0_SHIFT        20
  79 #define AHB_GATE_OFFSET_SPI0        20
  80
  81 #define SPI0_CLK_DIV_BY_2           0x1000
  82 #define SPI0_CLK_DIV_BY_4           0x1001
  83
  84 /*****************************************************************************/
  85
  86 /*
  87  * Allwinner A10/A20 SoCs were using pins PC0,PC1,PC2,PC23 for booting
  88  * from SPI Flash, everything else is using pins PC0,PC1,PC2,PC3.
  89  */
  90 static void spi0_pinmux_setup(unsigned int pin_function)
  91 {
  92         unsigned int pin;
  93
  94         for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(2); pin++)
  95                 sunxi_gpio_set_cfgpin(pin, pin_function);
  96
  97         if (IS_ENABLED(CONFIG_MACH_SUN4I) || IS_ENABLED(CONFIG_MACH_SUN7I))
  98                 sunxi_gpio_set_cfgpin(SUNXI_GPC(23), pin_function);
  99         else
 100                 sunxi_gpio_set_cfgpin(SUNXI_GPC(3), pin_function);
 101 }
 102
 103 static uintptr_t spi0_base_address(void)
 104 {
 105         if (!IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
 106                 return 0x01C05000;
 107
 108         return 0x01C68000;
 109 }
 110
 111 /*
 112  * Setup 6 MHz from OSC24M (because the BROM is doing the same).
 113  */
 114 static void spi0_enable_clock(void)
 115 {
 116         uintptr_t base = spi0_base_address();
 117
 118         /* Deassert SPI0 reset on SUN6I */
 119         if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
 120                 setbits_le32(SUN6I_BUS_SOFT_RST_REG0,
 121                              (1 << AHB_RESET_SPI0_SHIFT));
 122
 123         /* Open the SPI0 gate */
 124         setbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
 125
 126         /* Divide by 4 */
 127         writel(SPI0_CLK_DIV_BY_4, base + (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I) ?
 128                                   SUN6I_SPI0_CCTL : SUN4I_SPI0_CCTL));
 129         /* 24MHz from OSC24M */
 130         writel((1 << 31), CCM_SPI0_CLK);
 131
 132         if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) {
 133                 /* Enable SPI in the master mode and do a soft reset */
 134                 setbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
 135                              SUN6I_CTL_ENABLE | SUN6I_CTL_SRST);
 136                 /* Wait for completion */
 137                 while (readl(base + SUN6I_SPI0_GCR) & SUN6I_CTL_SRST)
 138                         ;
 139         } else {
 140                 /* Enable SPI in the master mode and reset FIFO */
 141                 setbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
 142                                                     SUN4I_CTL_ENABLE |
 143                                                     SUN4I_CTL_TF_RST |
 144                                                     SUN4I_CTL_RF_RST);
 145         }
 146 }
 147
 148 static void spi0_disable_clock(void)
 149 {
 150         uintptr_t base = spi0_base_address();
 151
 152         /* Disable the SPI0 controller */
 153         if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
 154                 clrbits_le32(base + SUN6I_SPI0_GCR, SUN6I_CTL_MASTER |
 155                                              SUN6I_CTL_ENABLE);
 156         else
 157                 clrbits_le32(base + SUN4I_SPI0_CTL, SUN4I_CTL_MASTER |
 158                                              SUN4I_CTL_ENABLE);
 159
 160         /* Disable the SPI0 clock */
 161         writel(0, CCM_SPI0_CLK);
 162
 163         /* Close the SPI0 gate */
 164         clrbits_le32(CCM_AHB_GATING0, (1 << AHB_GATE_OFFSET_SPI0));
 165
 166         /* Assert SPI0 reset on SUN6I */
 167         if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
 168                 clrbits_le32(SUN6I_BUS_SOFT_RST_REG0,
 169                              (1 << AHB_RESET_SPI0_SHIFT));
 170 }
 171
 172 static void spi0_init(void)
 173 {
 174         unsigned int pin_function = SUNXI_GPC_SPI0;
 175
 176         if (IS_ENABLED(CONFIG_MACH_SUN50I))
 177                 pin_function = SUN50I_GPC_SPI0;
 178
 179         spi0_pinmux_setup(pin_function);
 180         spi0_enable_clock();
 181 }
 182
 183 static void spi0_deinit(void)
 184 {
 185         /* New SoCs can disable pins, older could only set them as input */
 186         unsigned int pin_function = SUNXI_GPIO_INPUT;
 187         if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I))
 188                 pin_function = SUNXI_GPIO_DISABLE;
 189
 190         spi0_disable_clock();
 191         spi0_pinmux_setup(pin_function);
 192 }
 193
 194 /*****************************************************************************/
 195
 196 #define SPI_READ_MAX_SIZE 60 /* FIFO size, minus 4 bytes of the header */
 197
 198 static void sunxi_spi0_read_data(u8 *buf, u32 addr, u32 bufsize,
 199                                  ulong spi_ctl_reg,
 200                                  ulong spi_ctl_xch_bitmask,
 201                                  ulong spi_fifo_reg,
 202                                  ulong spi_tx_reg,
 203                                  ulong spi_rx_reg,
 204                                  ulong spi_bc_reg,
 205                                  ulong spi_tc_reg,
 206                                  ulong spi_bcc_reg)
 207 {
 208         writel(4 + bufsize, spi_bc_reg); /* Burst counter (total bytes) */
 209         writel(4, spi_tc_reg);           /* Transfer counter (bytes to send) */
 210         if (spi_bcc_reg)
 211                 writel(4, spi_bcc_reg);  /* SUN6I also needs this */
 212
 213         /* Send the Read Data Bytes (03h) command header */
 214         writeb(0x03, spi_tx_reg);
 215         writeb((u8)(addr >> 16), spi_tx_reg);
 216         writeb((u8)(addr >> 8), spi_tx_reg);
 217         writeb((u8)(addr), spi_tx_reg);
 218
 219         /* Start the data transfer */
 220         setbits_le32(spi_ctl_reg, spi_ctl_xch_bitmask);
 221
 222         /* Wait until everything is received in the RX FIFO */
 223         while ((readl(spi_fifo_reg) & 0x7F) < 4 + bufsize)
 224                 ;
 225
 226         /* Skip 4 bytes */
 227         readl(spi_rx_reg);
 228
 229         /* Read the data */
 230         while (bufsize-- > 0)
 231                 *buf++ = readb(spi_rx_reg);
 232
 233         /* tSHSL time is up to 100 ns in various SPI flash datasheets */
 234         udelay(1);
 235 }
 236
 237 static void spi0_read_data(void *buf, u32 addr, u32 len)
 238 {
 239         u8 *buf8 = buf;
 240         u32 chunk_len;
 241         uintptr_t base = spi0_base_address();
 242
 243         while (len > 0) {
 244                 chunk_len = len;
 245                 if (chunk_len > SPI_READ_MAX_SIZE)
 246                         chunk_len = SPI_READ_MAX_SIZE;
 247
 248                 if (IS_ENABLED(CONFIG_SUNXI_GEN_SUN6I)) {
 249                         sunxi_spi0_read_data(buf8, addr, chunk_len,
 250                                              base + SUN6I_SPI0_TCR,
 251                                              SUN6I_TCR_XCH,
 252                                              base + SUN6I_SPI0_FIFO_STA,
 253                                              base + SUN6I_SPI0_TXD,
 254                                              base + SUN6I_SPI0_RXD,
 255                                              base + SUN6I_SPI0_MBC,
 256                                              base + SUN6I_SPI0_MTC,
 257                                              base + SUN6I_SPI0_BCC);
 258                 } else {
 259                         sunxi_spi0_read_data(buf8, addr, chunk_len,
 260                                              base + SUN4I_SPI0_CTL,
 261                                              SUN4I_CTL_XCH,
 262                                              base + SUN4I_SPI0_FIFO_STA,
 263                                              base + SUN4I_SPI0_TX,
 264                                              base + SUN4I_SPI0_RX,
 265                                              base + SUN4I_SPI0_BC,
 266                                              base + SUN4I_SPI0_TC,
 267                                              0);
 268                 }
 269
 270                 len  -= chunk_len;
 271                 buf8 += chunk_len;
 272                 addr += chunk_len;
 273         }
 274 }
 275
 276 static ulong spi_load_read(struct spl_load_info *load, ulong sector,
 277                            ulong count, void *buf)
 278 {
 279         spi0_read_data(buf, sector, count);
 280
 281         return count;
 282 }
 283
 284 /*****************************************************************************/
 285
 286 static int spl_spi_load_image(struct spl_image_info *spl_image,
 287                               struct spl_boot_device *bootdev)
 288 {
 289         int ret = 0;
 290         struct image_header *header;
 291         header = (struct image_header *)(CONFIG_SYS_TEXT_BASE);
 292
 293         spi0_init();
 294
 295         spi0_read_data((void *)header, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40);
 296
 297         if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) &&
 298                 image_get_magic(header) == FDT_MAGIC) {
 299                 struct spl_load_info load;
 300
 301                 debug("Found FIT image\n");
 302                 load.dev = NULL;
 303                 load.priv = NULL;
 304                 load.filename = NULL;
 305                 load.bl_len = 1;
 306                 load.read = spi_load_read;
 307                 ret = spl_load_simple_fit(spl_image, &load,
 308                                           CONFIG_SYS_SPI_U_BOOT_OFFS, header);
 309         } else {
 310                 ret = spl_parse_image_header(spl_image, header);
 311                 if (ret)
 312                         return ret;
 313
 314                 spi0_read_data((void *)spl_image->load_addr,
 315                                CONFIG_SYS_SPI_U_BOOT_OFFS, spl_image->size);
 316         }
 317
 318         spi0_deinit();
 319
 320         return ret;
 321 }
 322 /* Use priorty 0 to override the default if it happens to be linked in */
 323 SPL_LOAD_IMAGE_METHOD("sunxi SPI", 0, BOOT_DEVICE_SPI, spl_spi_load_image);