SPDX: Convert all of our single license tags to Linux Kernel style
[oweals/u-boot.git] / arch / arm / mach-sunxi / p2wi.c
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Sunxi A31 Power Management Unit
4  *
5  * (C) Copyright 2013 Oliver Schinagl <oliver@schinagl.nl>
6  * http://linux-sunxi.org
7  *
8  * Based on sun6i sources and earlier U-Boot Allwiner A10 SPL work
9  *
10  * (C) Copyright 2006-2013
11  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
12  * Berg Xing <bergxing@allwinnertech.com>
13  * Tom Cubie <tangliang@allwinnertech.com>
14  */
15
16 #include <common.h>
17 #include <errno.h>
18 #include <asm/io.h>
19 #include <asm/arch/cpu.h>
20 #include <asm/arch/gpio.h>
21 #include <asm/arch/p2wi.h>
22 #include <asm/arch/prcm.h>
23 #include <asm/arch/clock.h>
24 #include <asm/arch/sys_proto.h>
25
26 void p2wi_init(void)
27 {
28         struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
29
30         /* Enable p2wi and PIO clk, and de-assert their resets */
31         prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_P2WI);
32
33         sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN6I_GPL0_R_P2WI_SCK);
34         sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN6I_GPL1_R_P2WI_SDA);
35
36         /* Reset p2wi controller and set clock to CLKIN(12)/8 = 1.5 MHz */
37         writel(P2WI_CTRL_RESET, &p2wi->ctrl);
38         sdelay(0x100);
39         writel(P2WI_CC_SDA_OUT_DELAY(1) | P2WI_CC_CLK_DIV(8),
40                &p2wi->cc);
41 }
42
43 int p2wi_change_to_p2wi_mode(u8 slave_addr, u8 ctrl_reg, u8 init_data)
44 {
45         struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
46         unsigned long tmo = timer_get_us() + 1000000;
47
48         writel(P2WI_PM_DEV_ADDR(slave_addr) |
49                P2WI_PM_CTRL_ADDR(ctrl_reg) |
50                P2WI_PM_INIT_DATA(init_data) |
51                P2WI_PM_INIT_SEND,
52                &p2wi->pm);
53
54         while ((readl(&p2wi->pm) & P2WI_PM_INIT_SEND)) {
55                 if (timer_get_us() > tmo)
56                         return -ETIME;
57         }
58
59         return 0;
60 }
61
62 static int p2wi_await_trans(void)
63 {
64         struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
65         unsigned long tmo = timer_get_us() + 1000000;
66         int ret;
67         u8 reg;
68
69         while (1) {
70                 reg = readl(&p2wi->status);
71                 if (reg & P2WI_STAT_TRANS_ERR) {
72                         ret = -EIO;
73                         break;
74                 }
75                 if (reg & P2WI_STAT_TRANS_DONE) {
76                         ret = 0;
77                         break;
78                 }
79                 if (timer_get_us() > tmo) {
80                         ret = -ETIME;
81                         break;
82                 }
83         }
84         writel(reg, &p2wi->status); /* Clear status bits */
85         return ret;
86 }
87
88 int p2wi_read(const u8 addr, u8 *data)
89 {
90         struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
91         int ret;
92
93         writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
94         writel(P2WI_DATA_NUM_BYTES(1) |
95                P2WI_DATA_NUM_BYTES_READ, &p2wi->numbytes);
96         writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
97         writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
98
99         ret = p2wi_await_trans();
100
101         *data = readl(&p2wi->data0) & P2WI_DATA_BYTE_1_MASK;
102         return ret;
103 }
104
105 int p2wi_write(const u8 addr, u8 data)
106 {
107         struct sunxi_p2wi_reg *p2wi = (struct sunxi_p2wi_reg *)SUN6I_P2WI_BASE;
108
109         writel(P2WI_DATADDR_BYTE_1(addr), &p2wi->dataddr0);
110         writel(P2WI_DATA_BYTE_1(data), &p2wi->data0);
111         writel(P2WI_DATA_NUM_BYTES(1), &p2wi->numbytes);
112         writel(P2WI_STAT_TRANS_DONE, &p2wi->status);
113         writel(P2WI_CTRL_TRANS_START, &p2wi->ctrl);
114
115         return p2wi_await_trans();
116 }