arch/arm/mach-sunxi/dram_sun8i_h3.c

   1 /*
   2  * sun8i H3 platform dram controller init
   3  *
   4  * (C) Copyright 2007-2015 Allwinner Technology Co.
   5  *                         Jerry Wang <wangflord@allwinnertech.com>
   6  * (C) Copyright 2015      Vishnu Patekar <vishnupatekar0510@gmail.com>
   7  * (C) Copyright 2015      Hans de Goede <hdegoede@redhat.com>
   8  * (C) Copyright 2015      Jens Kuske <jenskuske@gmail.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12 #include <common.h>
  13 #include <asm/io.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/dram.h>
  16 #include <linux/kconfig.h>
  17
  18 struct dram_para {
  19         u32 read_delays;
  20         u32 write_delays;
  21         u16 page_size;
  22         u8 bus_width;
  23         u8 dual_rank;
  24         u8 row_bits;
  25 };
  26
  27 static inline int ns_to_t(int nanoseconds)
  28 {
  29         const unsigned int ctrl_freq = CONFIG_DRAM_CLK / 2;
  30
  31         return DIV_ROUND_UP(ctrl_freq * nanoseconds, 1000);
  32 }
  33
  34 static u32 bin_to_mgray(int val)
  35 {
  36         static const u8 lookup_table[32] = {
  37                 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
  38                 0x0c, 0x0d, 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09,
  39                 0x18, 0x19, 0x1a, 0x1b, 0x1e, 0x1f, 0x1c, 0x1d,
  40                 0x14, 0x15, 0x16, 0x17, 0x12, 0x13, 0x10, 0x11,
  41         };
  42
  43         return lookup_table[clamp(val, 0, 31)];
  44 }
  45
  46 static int mgray_to_bin(u32 val)
  47 {
  48         static const u8 lookup_table[32] = {
  49                 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05,
  50                 0x0e, 0x0f, 0x0c, 0x0d, 0x08, 0x09, 0x0a, 0x0b,
  51                 0x1e, 0x1f, 0x1c, 0x1d, 0x18, 0x19, 0x1a, 0x1b,
  52                 0x10, 0x11, 0x12, 0x13, 0x16, 0x17, 0x14, 0x15,
  53         };
  54
  55         return lookup_table[val & 0x1f];
  56 }
  57
  58 static void mctl_phy_init(u32 val)
  59 {
  60         struct sunxi_mctl_ctl_reg * const mctl_ctl =
  61                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  62
  63         writel(val | PIR_INIT, &mctl_ctl->pir);
  64         mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1);
  65 }
  66
  67 static void mctl_dq_delay(u32 read, u32 write)
  68 {
  69         struct sunxi_mctl_ctl_reg * const mctl_ctl =
  70                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
  71         int i, j;
  72         u32 val;
  73
  74         for (i = 0; i < 4; i++) {
  75                 val = DATX_IOCR_WRITE_DELAY((write >> (i * 4)) & 0xf) |
  76                       DATX_IOCR_READ_DELAY(((read >> (i * 4)) & 0xf) * 2);
  77
  78                 for (j = DATX_IOCR_DQ(0); j <= DATX_IOCR_DM; j++)
  79                         writel(val, &mctl_ctl->datx[i].iocr[j]);
  80         }
  81
  82         clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
  83
  84         for (i = 0; i < 4; i++) {
  85                 val = DATX_IOCR_WRITE_DELAY((write >> (16 + i * 4)) & 0xf) |
  86                       DATX_IOCR_READ_DELAY((read >> (16 + i * 4)) & 0xf);
  87
  88                 writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQS]);
  89                 writel(val, &mctl_ctl->datx[i].iocr[DATX_IOCR_DQSN]);
  90         }
  91
  92         setbits_le32(&mctl_ctl->pgcr[0], 1 << 26);
  93
  94         udelay(1);
  95 }
  96
  97 static void mctl_set_master_priority(void)
  98 {
  99         struct sunxi_mctl_com_reg * const mctl_com =
 100                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 101
 102         /* enable bandwidth limit windows and set windows size 1us */
 103         writel(0x00010190, &mctl_com->bwcr);
 104
 105         /* set cpu high priority */
 106         writel(0x00000001, &mctl_com->mapr);
 107
 108         writel(0x0200000d, &mctl_com->mcr[0][0]);
 109         writel(0x00800100, &mctl_com->mcr[0][1]);
 110         writel(0x06000009, &mctl_com->mcr[1][0]);
 111         writel(0x01000400, &mctl_com->mcr[1][1]);
 112         writel(0x0200000d, &mctl_com->mcr[2][0]);
 113         writel(0x00600100, &mctl_com->mcr[2][1]);
 114         writel(0x0100000d, &mctl_com->mcr[3][0]);
 115         writel(0x00200080, &mctl_com->mcr[3][1]);
 116         writel(0x07000009, &mctl_com->mcr[4][0]);
 117         writel(0x01000640, &mctl_com->mcr[4][1]);
 118         writel(0x0100000d, &mctl_com->mcr[5][0]);
 119         writel(0x00200080, &mctl_com->mcr[5][1]);
 120         writel(0x01000009, &mctl_com->mcr[6][0]);
 121         writel(0x00400080, &mctl_com->mcr[6][1]);
 122         writel(0x0100000d, &mctl_com->mcr[7][0]);
 123         writel(0x00400080, &mctl_com->mcr[7][1]);
 124         writel(0x0100000d, &mctl_com->mcr[8][0]);
 125         writel(0x00400080, &mctl_com->mcr[8][1]);
 126         writel(0x04000009, &mctl_com->mcr[9][0]);
 127         writel(0x00400100, &mctl_com->mcr[9][1]);
 128         writel(0x2000030d, &mctl_com->mcr[10][0]);
 129         writel(0x04001800, &mctl_com->mcr[10][1]);
 130         writel(0x04000009, &mctl_com->mcr[11][0]);
 131         writel(0x00400120, &mctl_com->mcr[11][1]);
 132 }
 133
 134 static void mctl_set_timing_params(struct dram_para *para)
 135 {
 136         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 137                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 138
 139         u8 tccd         = 2;
 140         u8 tfaw         = ns_to_t(50);
 141         u8 trrd         = max(ns_to_t(10), 4);
 142         u8 trcd         = ns_to_t(15);
 143         u8 trc          = ns_to_t(53);
 144         u8 txp          = max(ns_to_t(8), 3);
 145         u8 twtr         = max(ns_to_t(8), 4);
 146         u8 trtp         = max(ns_to_t(8), 4);
 147         u8 twr          = max(ns_to_t(15), 3);
 148         u8 trp          = ns_to_t(15);
 149         u8 tras         = ns_to_t(38);
 150         u16 trefi       = ns_to_t(7800) / 32;
 151         u16 trfc        = ns_to_t(350);
 152
 153         u8 tmrw         = 0;
 154         u8 tmrd         = 4;
 155         u8 tmod         = 12;
 156         u8 tcke         = 3;
 157         u8 tcksrx       = 5;
 158         u8 tcksre       = 5;
 159         u8 tckesr       = 4;
 160         u8 trasmax      = 24;
 161
 162         u8 tcl          = 6; /* CL 12 */
 163         u8 tcwl         = 4; /* CWL 8 */
 164         u8 t_rdata_en   = 4;
 165         u8 wr_latency   = 2;
 166
 167         u32 tdinit0     = (500 * CONFIG_DRAM_CLK) + 1;          /* 500us */
 168         u32 tdinit1     = (360 * CONFIG_DRAM_CLK) / 1000 + 1;   /* 360ns */
 169         u32 tdinit2     = (200 * CONFIG_DRAM_CLK) + 1;          /* 200us */
 170         u32 tdinit3     = (1 * CONFIG_DRAM_CLK) + 1;            /* 1us */
 171
 172         u8 twtp         = tcwl + 2 + twr;       /* WL + BL / 2 + tWR */
 173         u8 twr2rd       = tcwl + 2 + twtr;      /* WL + BL / 2 + tWTR */
 174         u8 trd2wr       = tcl + 2 + 1 - tcwl;   /* RL + BL / 2 + 2 - WL */
 175
 176         /* set mode register */
 177         writel(0x1c70, &mctl_ctl->mr[0]);       /* CL=11, WR=12 */
 178         writel(0x40, &mctl_ctl->mr[1]);
 179         writel(0x18, &mctl_ctl->mr[2]);         /* CWL=8 */
 180         writel(0x0, &mctl_ctl->mr[3]);
 181
 182         /* set DRAM timing */
 183         writel(DRAMTMG0_TWTP(twtp) | DRAMTMG0_TFAW(tfaw) |
 184                DRAMTMG0_TRAS_MAX(trasmax) | DRAMTMG0_TRAS(tras),
 185                &mctl_ctl->dramtmg[0]);
 186         writel(DRAMTMG1_TXP(txp) | DRAMTMG1_TRTP(trtp) | DRAMTMG1_TRC(trc),
 187                &mctl_ctl->dramtmg[1]);
 188         writel(DRAMTMG2_TCWL(tcwl) | DRAMTMG2_TCL(tcl) |
 189                DRAMTMG2_TRD2WR(trd2wr) | DRAMTMG2_TWR2RD(twr2rd),
 190                &mctl_ctl->dramtmg[2]);
 191         writel(DRAMTMG3_TMRW(tmrw) | DRAMTMG3_TMRD(tmrd) | DRAMTMG3_TMOD(tmod),
 192                &mctl_ctl->dramtmg[3]);
 193         writel(DRAMTMG4_TRCD(trcd) | DRAMTMG4_TCCD(tccd) | DRAMTMG4_TRRD(trrd) |
 194                DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]);
 195         writel(DRAMTMG5_TCKSRX(tcksrx) | DRAMTMG5_TCKSRE(tcksre) |
 196                DRAMTMG5_TCKESR(tckesr) | DRAMTMG5_TCKE(tcke),
 197                &mctl_ctl->dramtmg[5]);
 198
 199         /* set two rank timing */
 200         clrsetbits_le32(&mctl_ctl->dramtmg[8], (0xff << 8) | (0xff << 0),
 201                         (0x66 << 8) | (0x10 << 0));
 202
 203         /* set PHY interface timing, write latency and read latency configure */
 204         writel((0x2 << 24) | (t_rdata_en << 16) | (0x1 << 8) |
 205                (wr_latency << 0), &mctl_ctl->pitmg[0]);
 206
 207         /* set PHY timing, PTR0-2 use default */
 208         writel(PTR3_TDINIT0(tdinit0) | PTR3_TDINIT1(tdinit1), &mctl_ctl->ptr[3]);
 209         writel(PTR4_TDINIT2(tdinit2) | PTR4_TDINIT3(tdinit3), &mctl_ctl->ptr[4]);
 210
 211         /* set refresh timing */
 212         writel(RFSHTMG_TREFI(trefi) | RFSHTMG_TRFC(trfc), &mctl_ctl->rfshtmg);
 213 }
 214
 215 static void mctl_zq_calibration(struct dram_para *para)
 216 {
 217         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 218                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 219
 220         if ((readl(SUNXI_SRAMC_BASE + 0x24) & 0xff) == 0 &&
 221             (readl(SUNXI_SRAMC_BASE + 0xf0) & 0x1) == 0) {
 222                 u32 reg_val;
 223
 224                 clrsetbits_le32(&mctl_ctl->zqcr, 0xffff,
 225                                 CONFIG_DRAM_ZQ & 0xffff);
 226
 227                 writel(PIR_CLRSR, &mctl_ctl->pir);
 228                 mctl_phy_init(PIR_ZCAL);
 229
 230                 reg_val = readl(&mctl_ctl->zqdr[0]);
 231                 reg_val &= (0x1f << 16) | (0x1f << 0);
 232                 reg_val |= reg_val << 8;
 233                 writel(reg_val, &mctl_ctl->zqdr[0]);
 234
 235                 reg_val = readl(&mctl_ctl->zqdr[1]);
 236                 reg_val &= (0x1f << 16) | (0x1f << 0);
 237                 reg_val |= reg_val << 8;
 238                 writel(reg_val, &mctl_ctl->zqdr[1]);
 239                 writel(reg_val, &mctl_ctl->zqdr[2]);
 240         } else {
 241                 int i;
 242                 u16 zq_val[6];
 243                 u8 val;
 244
 245                 writel(0x0a0a0a0a, &mctl_ctl->zqdr[2]);
 246
 247                 for (i = 0; i < 6; i++) {
 248                         u8 zq = (CONFIG_DRAM_ZQ >> (i * 4)) & 0xf;
 249
 250                         writel((zq << 20) | (zq << 16) | (zq << 12) |
 251                                         (zq << 8) | (zq << 4) | (zq << 0),
 252                                         &mctl_ctl->zqcr);
 253
 254                         writel(PIR_CLRSR, &mctl_ctl->pir);
 255                         mctl_phy_init(PIR_ZCAL);
 256
 257                         zq_val[i] = readl(&mctl_ctl->zqdr[0]) & 0xff;
 258                         writel(REPEAT_BYTE(zq_val[i]), &mctl_ctl->zqdr[2]);
 259
 260                         writel(PIR_CLRSR, &mctl_ctl->pir);
 261                         mctl_phy_init(PIR_ZCAL);
 262
 263                         val = readl(&mctl_ctl->zqdr[0]) >> 24;
 264                         zq_val[i] |= bin_to_mgray(mgray_to_bin(val) - 1) << 8;
 265                 }
 266
 267                 writel((zq_val[1] << 16) | zq_val[0], &mctl_ctl->zqdr[0]);
 268                 writel((zq_val[3] << 16) | zq_val[2], &mctl_ctl->zqdr[1]);
 269                 writel((zq_val[5] << 16) | zq_val[4], &mctl_ctl->zqdr[2]);
 270         }
 271 }
 272
 273 static void mctl_set_cr(struct dram_para *para)
 274 {
 275         struct sunxi_mctl_com_reg * const mctl_com =
 276                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 277
 278         writel(MCTL_CR_BL8 | MCTL_CR_2T | MCTL_CR_DDR3 | MCTL_CR_INTERLEAVED |
 279                MCTL_CR_EIGHT_BANKS | MCTL_CR_BUS_WIDTH(para->bus_width) |
 280                (para->dual_rank ? MCTL_CR_DUAL_RANK : MCTL_CR_SINGLE_RANK) |
 281                MCTL_CR_PAGE_SIZE(para->page_size) |
 282                MCTL_CR_ROW_BITS(para->row_bits), &mctl_com->cr);
 283 }
 284
 285 static void mctl_sys_init(struct dram_para *para)
 286 {
 287         struct sunxi_ccm_reg * const ccm =
 288                         (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 289         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 290                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 291
 292         clrbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
 293         clrbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
 294         clrbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
 295         clrbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
 296         clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
 297         udelay(10);
 298
 299         clrbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
 300         udelay(1000);
 301
 302         clock_set_pll5(CONFIG_DRAM_CLK * 2 * 1000000, false);
 303         clrsetbits_le32(&ccm->dram_clk_cfg,
 304                         CCM_DRAMCLK_CFG_DIV_MASK | CCM_DRAMCLK_CFG_SRC_MASK,
 305                         CCM_DRAMCLK_CFG_DIV(1) | CCM_DRAMCLK_CFG_SRC_PLL5 |
 306                         CCM_DRAMCLK_CFG_UPD);
 307         mctl_await_completion(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_UPD, 0);
 308
 309         setbits_le32(&ccm->ahb_reset0_cfg, 1 << AHB_RESET_OFFSET_MCTL);
 310         setbits_le32(&ccm->ahb_gate0, 1 << AHB_GATE_OFFSET_MCTL);
 311         setbits_le32(&ccm->mbus_reset, CCM_MBUS_RESET_RESET);
 312         setbits_le32(&ccm->mbus0_clk_cfg, MBUS_CLK_GATE);
 313
 314         setbits_le32(&ccm->dram_clk_cfg, CCM_DRAMCLK_CFG_RST);
 315         udelay(10);
 316
 317         writel(0xc00e, &mctl_ctl->clken);
 318         udelay(500);
 319 }
 320
 321 static int mctl_channel_init(struct dram_para *para)
 322 {
 323         struct sunxi_mctl_com_reg * const mctl_com =
 324                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 325         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 326                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 327
 328         unsigned int i;
 329
 330         mctl_set_cr(para);
 331         mctl_set_timing_params(para);
 332         mctl_set_master_priority();
 333
 334         /* setting VTC, default disable all VT */
 335         clrbits_le32(&mctl_ctl->pgcr[0], (1 << 30) | 0x3f);
 336         clrsetbits_le32(&mctl_ctl->pgcr[1], 1 << 24, 1 << 26);
 337
 338         /* increase DFI_PHY_UPD clock */
 339         writel(PROTECT_MAGIC, &mctl_com->protect);
 340         udelay(100);
 341         clrsetbits_le32(&mctl_ctl->upd2, 0xfff << 16, 0x50 << 16);
 342         writel(0x0, &mctl_com->protect);
 343         udelay(100);
 344
 345         /* set dramc odt */
 346         for (i = 0; i < 4; i++)
 347                 clrsetbits_le32(&mctl_ctl->datx[i].gcr, (0x3 << 4) |
 348                                 (0x1 << 1) | (0x3 << 2) | (0x3 << 12) |
 349                                 (0x3 << 14),
 350                                 IS_ENABLED(CONFIG_DRAM_ODT_EN) ? 0x0 : 0x2);
 351
 352         /* AC PDR should always ON */
 353         setbits_le32(&mctl_ctl->aciocr, 0x1 << 1);
 354
 355         /* set DQS auto gating PD mode */
 356         setbits_le32(&mctl_ctl->pgcr[2], 0x3 << 6);
 357
 358         /* dx ddr_clk & hdr_clk dynamic mode */
 359         clrbits_le32(&mctl_ctl->pgcr[0], (0x3 << 14) | (0x3 << 12));
 360
 361         /* dphy & aphy phase select 270 degree */
 362         clrsetbits_le32(&mctl_ctl->pgcr[2], (0x3 << 10) | (0x3 << 8),
 363                         (0x1 << 10) | (0x2 << 8));
 364
 365         /* set half DQ */
 366         if (para->bus_width != 32) {
 367                 writel(0x0, &mctl_ctl->datx[2].gcr);
 368                 writel(0x0, &mctl_ctl->datx[3].gcr);
 369         }
 370
 371         /* data training configuration */
 372         clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24,
 373                         (para->dual_rank ? 0x3 : 0x1) << 24);
 374
 375
 376         if (para->read_delays || para->write_delays) {
 377                 mctl_dq_delay(para->read_delays, para->write_delays);
 378                 udelay(50);
 379         }
 380
 381         mctl_zq_calibration(para);
 382
 383         mctl_phy_init(PIR_PLLINIT | PIR_DCAL | PIR_PHYRST | PIR_DRAMRST |
 384                       PIR_DRAMINIT | PIR_QSGATE);
 385
 386         /* detect ranks and bus width */
 387         if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20)) {
 388                 /* only one rank */
 389                 if (((readl(&mctl_ctl->datx[0].gsr[0]) >> 24) & 0x2) ||
 390                     ((readl(&mctl_ctl->datx[1].gsr[0]) >> 24) & 0x2)) {
 391                         clrsetbits_le32(&mctl_ctl->dtcr, 0xf << 24, 0x1 << 24);
 392                         para->dual_rank = 0;
 393                 }
 394
 395                 /* only half DQ width */
 396                 if (((readl(&mctl_ctl->datx[2].gsr[0]) >> 24) & 0x1) ||
 397                     ((readl(&mctl_ctl->datx[3].gsr[0]) >> 24) & 0x1)) {
 398                         writel(0x0, &mctl_ctl->datx[2].gcr);
 399                         writel(0x0, &mctl_ctl->datx[3].gcr);
 400                         para->bus_width = 16;
 401                 }
 402
 403                 mctl_set_cr(para);
 404                 udelay(20);
 405
 406                 /* re-train */
 407                 mctl_phy_init(PIR_QSGATE);
 408                 if (readl(&mctl_ctl->pgsr[0]) & (0xfe << 20))
 409                         return 1;
 410         }
 411
 412         /* check the dramc status */
 413         mctl_await_completion(&mctl_ctl->statr, 0x1, 0x1);
 414
 415         /* liuke added for refresh debug */
 416         setbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
 417         udelay(10);
 418         clrbits_le32(&mctl_ctl->rfshctl0, 0x1 << 31);
 419         udelay(10);
 420
 421         /* set PGCR3, CKE polarity */
 422         writel(0x00aa0060, &mctl_ctl->pgcr[3]);
 423
 424         /* power down zq calibration module for power save */
 425         setbits_le32(&mctl_ctl->zqcr, ZQCR_PWRDOWN);
 426
 427         /* enable master access */
 428         writel(0xffffffff, &mctl_com->maer);
 429
 430         return 0;
 431 }
 432
 433 static void mctl_auto_detect_dram_size(struct dram_para *para)
 434 {
 435         /* detect row address bits */
 436         para->page_size = 512;
 437         para->row_bits = 16;
 438         mctl_set_cr(para);
 439
 440         for (para->row_bits = 11; para->row_bits < 16; para->row_bits++)
 441                 if (mctl_mem_matches((1 << (para->row_bits + 3)) * para->page_size))
 442                         break;
 443
 444         /* detect page size */
 445         para->page_size = 8192;
 446         mctl_set_cr(para);
 447
 448         for (para->page_size = 512; para->page_size < 8192; para->page_size *= 2)
 449                 if (mctl_mem_matches(para->page_size))
 450                         break;
 451 }
 452
 453 unsigned long sunxi_dram_init(void)
 454 {
 455         struct sunxi_mctl_com_reg * const mctl_com =
 456                         (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
 457         struct sunxi_mctl_ctl_reg * const mctl_ctl =
 458                         (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
 459
 460         struct dram_para para = {
 461                 .read_delays = 0x00007979,      /* dram_tpr12 */
 462                 .write_delays = 0x6aaa0000,     /* dram_tpr11 */
 463                 .dual_rank = 0,
 464                 .bus_width = 32,
 465                 .row_bits = 15,
 466                 .page_size = 4096,
 467         };
 468
 469         mctl_sys_init(&para);
 470         if (mctl_channel_init(&para))
 471                 return 0;
 472
 473         if (para.dual_rank)
 474                 writel(0x00000303, &mctl_ctl->odtmap);
 475         else
 476                 writel(0x00000201, &mctl_ctl->odtmap);
 477         udelay(1);
 478
 479         /* odt delay */
 480         writel(0x0c000400, &mctl_ctl->odtcfg);
 481
 482         /* clear credit value */
 483         setbits_le32(&mctl_com->cccr, 1 << 31);
 484         udelay(10);
 485
 486         mctl_auto_detect_dram_size(&para);
 487         mctl_set_cr(&para);
 488
 489         return (1 << (para.row_bits + 3)) * para.page_size *
 490                                                 (para.dual_rank ? 2 : 1);
 491 }