2 * sun50i H6 platform dram controller init
4 * (C) Copyright 2017 Icenowy Zheng <icenowy@aosc.io>
6 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/dram.h>
12 #include <asm/arch/cpu.h>
13 #include <linux/bitops.h>
14 #include <linux/kconfig.h>
17 * The DRAM controller structure on H6 is similar to the ones on A23/A80:
18 * they all contains 3 parts, COM, CTL and PHY. (As a note on A33/A83T/H3/A64
19 * /H5/R40 CTL and PHY is composed).
21 * COM is allwinner-specific. On H6, the address mapping function is moved
22 * from COM to CTL (with the standard ADDRMAP registers on DesignWare memory
25 * CTL (controller) and PHY is from DesignWare.
27 * The CTL part is a bit similar to the one on A23/A80 (because they all
28 * originate from DesignWare), but gets more registers added.
30 * The PHY part is quite new, not seen in any previous Allwinner SoCs, and
31 * not seen on other SoCs in U-Boot. The only SoC that is also known to have
32 * similar PHY is ZynqMP.
35 static void mctl_sys_init(struct dram_para *para);
36 static void mctl_com_init(struct dram_para *para);
37 static void mctl_channel_init(struct dram_para *para);
39 static void mctl_core_init(struct dram_para *para)
44 case SUNXI_DRAM_TYPE_LPDDR3:
45 case SUNXI_DRAM_TYPE_DDR3:
46 mctl_set_timing_params(para);
49 panic("Unsupported DRAM type!");
51 mctl_channel_init(para);
54 /* PHY initialisation */
55 static void mctl_phy_pir_init(u32 val)
57 struct sunxi_mctl_phy_reg * const mctl_phy =
58 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
60 writel(val, &mctl_phy->pir);
61 writel(val | BIT(0), &mctl_phy->pir); /* Start initialisation. */
62 mctl_await_completion(&mctl_phy->pgsr[0], BIT(0), BIT(0));
92 inline void mbus_configure_port(u8 port,
102 struct sunxi_mctl_com_reg * const mctl_com =
103 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
105 const u32 cfg0 = ( (bwlimit ? (1 << 0) : 0)
106 | (priority ? (1 << 1) : 0)
108 | ((waittime & 0xf) << 4)
109 | ((acs & 0xff) << 8)
111 const u32 cfg1 = ((u32)bwl2 << 16) | (bwl1 & 0xffff);
113 debug("MBUS port %d cfg0 %08x cfg1 %08x\n", port, cfg0, cfg1);
114 writel(cfg0, &mctl_com->master[port].cfg0);
115 writel(cfg1, &mctl_com->master[port].cfg1);
118 #define MBUS_CONF(port, bwlimit, qos, acs, bwl0, bwl1, bwl2) \
119 mbus_configure_port(MBUS_PORT_ ## port, bwlimit, false, \
120 MBUS_QOS_ ## qos, 0, acs, bwl0, bwl1, bwl2)
122 static void mctl_set_master_priority(void)
124 struct sunxi_mctl_com_reg * const mctl_com =
125 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
127 /* enable bandwidth limit windows and set windows size 1us */
128 writel(399, &mctl_com->tmr);
129 writel(BIT(16), &mctl_com->bwcr);
131 MBUS_CONF( CPU, true, HIGHEST, 0, 256, 128, 100);
132 MBUS_CONF( GPU, true, HIGH, 0, 1536, 1400, 256);
133 MBUS_CONF( MAHB, true, HIGHEST, 0, 512, 256, 96);
134 MBUS_CONF( DMA, true, HIGH, 0, 256, 100, 80);
135 MBUS_CONF( VE, true, HIGH, 2, 8192, 5500, 5000);
136 MBUS_CONF( CE, true, HIGH, 2, 100, 64, 32);
137 MBUS_CONF( TSC0, true, HIGH, 2, 100, 64, 32);
138 MBUS_CONF(NDFC0, true, HIGH, 0, 256, 128, 64);
139 MBUS_CONF( CSI0, true, HIGH, 0, 256, 128, 100);
140 MBUS_CONF( DI0, true, HIGH, 0, 1024, 256, 64);
141 MBUS_CONF(DE300, true, HIGHEST, 6, 8192, 2800, 2400);
142 MBUS_CONF(IOMMU, true, HIGHEST, 0, 100, 64, 32);
143 MBUS_CONF( VE2, true, HIGH, 2, 8192, 5500, 5000);
144 MBUS_CONF( USB3, true, HIGH, 0, 256, 128, 64);
145 MBUS_CONF( PCIE, true, HIGH, 2, 100, 64, 32);
146 MBUS_CONF( VP9, true, HIGH, 2, 8192, 5500, 5000);
147 MBUS_CONF(HDCP2, true, HIGH, 2, 100, 64, 32);
150 static void mctl_sys_init(struct dram_para *para)
152 struct sunxi_ccm_reg * const ccm =
153 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
154 struct sunxi_mctl_com_reg * const mctl_com =
155 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
156 struct sunxi_mctl_ctl_reg * const mctl_ctl =
157 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
159 /* Put all DRAM-related blocks to reset state */
160 clrbits_le32(&ccm->mbus_cfg, MBUS_ENABLE | MBUS_RESET);
161 clrbits_le32(&ccm->dram_gate_reset, BIT(0));
163 writel(0, &ccm->dram_gate_reset);
164 clrbits_le32(&ccm->pll5_cfg, CCM_PLL5_CTRL_EN);
165 clrbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
169 /* Set PLL5 rate to doubled DRAM clock rate */
170 writel(CCM_PLL5_CTRL_EN | CCM_PLL5_LOCK_EN |
171 CCM_PLL5_CTRL_N(para->clk * 2 / 24 - 1), &ccm->pll5_cfg);
172 mctl_await_completion(&ccm->pll5_cfg, CCM_PLL5_LOCK, CCM_PLL5_LOCK);
174 /* Configure DRAM mod clock */
175 writel(DRAM_CLK_SRC_PLL5, &ccm->dram_clk_cfg);
176 setbits_le32(&ccm->dram_clk_cfg, DRAM_CLK_UPDATE);
177 writel(BIT(RESET_SHIFT), &ccm->dram_gate_reset);
179 setbits_le32(&ccm->dram_gate_reset, BIT(0));
181 /* Disable all channels */
182 writel(0, &mctl_com->maer0);
183 writel(0, &mctl_com->maer1);
184 writel(0, &mctl_com->maer2);
186 /* Configure MBUS and enable DRAM mod reset */
187 setbits_le32(&ccm->mbus_cfg, MBUS_RESET);
188 setbits_le32(&ccm->mbus_cfg, MBUS_ENABLE);
189 setbits_le32(&ccm->dram_clk_cfg, DRAM_MOD_RESET);
192 /* Unknown hack from the BSP, which enables access of mctl_ctl regs */
193 writel(0x8000, &mctl_ctl->unk_0x00c);
196 static void mctl_set_addrmap(struct dram_para *para)
198 struct sunxi_mctl_ctl_reg * const mctl_ctl =
199 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
200 u8 cols = para->cols;
201 u8 rows = para->rows;
202 u8 ranks = para->ranks;
206 mctl_ctl->addrmap[0] = rows + cols - 3;
208 mctl_ctl->addrmap[0] = 0x1F;
210 /* Banks, hardcoded to 8 banks now */
211 mctl_ctl->addrmap[1] = (cols - 2) | (cols - 2) << 8 | (cols - 2) << 16;
214 mctl_ctl->addrmap[2] = 0;
217 mctl_ctl->addrmap[3] = 0x1F1F0000;
218 mctl_ctl->addrmap[4] = 0x1F1F;
221 mctl_ctl->addrmap[3] = 0x1F000000;
222 mctl_ctl->addrmap[4] = 0x1F1F;
225 mctl_ctl->addrmap[3] = 0;
226 mctl_ctl->addrmap[4] = 0x1F1F;
229 mctl_ctl->addrmap[3] = 0;
230 mctl_ctl->addrmap[4] = 0x1F00;
233 mctl_ctl->addrmap[3] = 0;
234 mctl_ctl->addrmap[4] = 0;
237 panic("Unsupported DRAM configuration: column number invalid\n");
241 mctl_ctl->addrmap[5] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
244 mctl_ctl->addrmap[6] = (cols - 3) | 0x0F0F0F00;
245 mctl_ctl->addrmap[7] = 0x0F0F;
248 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | 0x0F0F0000;
249 mctl_ctl->addrmap[7] = 0x0F0F;
252 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | 0x0F000000;
253 mctl_ctl->addrmap[7] = 0x0F0F;
256 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
257 mctl_ctl->addrmap[7] = 0x0F0F;
260 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
261 mctl_ctl->addrmap[7] = (cols - 3) | 0x0F00;
264 mctl_ctl->addrmap[6] = (cols - 3) | ((cols - 3) << 8) | ((cols - 3) << 16) | ((cols - 3) << 24);
265 mctl_ctl->addrmap[7] = (cols - 3) | ((cols - 3) << 8);
268 panic("Unsupported DRAM configuration: row number invalid\n");
271 /* Bank groups, DDR4 only */
272 mctl_ctl->addrmap[8] = 0x3F3F;
275 static void mctl_com_init(struct dram_para *para)
277 struct sunxi_mctl_com_reg * const mctl_com =
278 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
279 struct sunxi_mctl_ctl_reg * const mctl_ctl =
280 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
281 struct sunxi_mctl_phy_reg * const mctl_phy =
282 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
285 mctl_set_addrmap(para);
287 setbits_le32(&mctl_com->cr, BIT(31));
289 /* The bonding ID seems to be always 7. */
290 if (readl(SUNXI_SIDC_BASE + 0x100) == 7) /* bonding ID */
291 clrbits_le32(&mctl_com->cr, BIT(27));
292 else if (readl(SUNXI_SIDC_BASE + 0x100) == 3)
293 setbits_le32(&mctl_com->cr, BIT(27));
297 else if (para->clk > 246)
301 clrsetbits_le32(&mctl_com->unk_0x008, 0x3f00, reg_val);
303 /* TODO: half DQ, DDR4 */
304 reg_val = MSTR_BUSWIDTH_FULL | MSTR_BURST_LENGTH(8) |
305 MSTR_ACTIVE_RANKS(para->ranks);
306 if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
307 reg_val |= MSTR_DEVICETYPE_LPDDR3;
308 if (para->type == SUNXI_DRAM_TYPE_DDR3)
309 reg_val |= MSTR_DEVICETYPE_DDR3 | MSTR_2TMODE;
310 writel(reg_val | BIT(31), &mctl_ctl->mstr);
312 if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
313 reg_val = DCR_LPDDR3 | DCR_DDR8BANK;
314 if (para->type == SUNXI_DRAM_TYPE_DDR3)
315 reg_val = DCR_DDR3 | DCR_DDR8BANK | DCR_DDR2T;
316 writel(reg_val | 0x400, &mctl_phy->dcr);
318 if (para->ranks == 2)
319 writel(0x0303, &mctl_ctl->odtmap);
321 writel(0x0201, &mctl_ctl->odtmap);
324 if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
325 tmp = para->clk * 7 / 2000;
327 reg_val |= (tmp + 7) << 24;
328 reg_val |= (((para->clk < 400) ? 3 : 4) - tmp) << 16;
329 } else if (para->type == SUNXI_DRAM_TYPE_DDR3) {
330 reg_val = 0x06000400; /* TODO?: Use CL - CWL value in [7:0] */
332 panic("Only (LP)DDR3 supported (type = %d)\n", para->type);
334 writel(reg_val, &mctl_ctl->odtcfg);
339 static void mctl_bit_delay_set(struct dram_para *para)
341 struct sunxi_mctl_phy_reg * const mctl_phy =
342 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
346 for (i = 0; i < 4; i++) {
347 val = readl(&mctl_phy->dx[i].bdlr0);
348 for (j = 0; j < 4; j++)
349 val += para->dx_write_delays[i][j] << (j * 8);
350 writel(val, &mctl_phy->dx[i].bdlr0);
352 val = readl(&mctl_phy->dx[i].bdlr1);
353 for (j = 0; j < 4; j++)
354 val += para->dx_write_delays[i][j + 4] << (j * 8);
355 writel(val, &mctl_phy->dx[i].bdlr1);
357 val = readl(&mctl_phy->dx[i].bdlr2);
358 for (j = 0; j < 4; j++)
359 val += para->dx_write_delays[i][j + 8] << (j * 8);
360 writel(val, &mctl_phy->dx[i].bdlr2);
362 clrbits_le32(&mctl_phy->pgcr[0], BIT(26));
364 for (i = 0; i < 4; i++) {
365 val = readl(&mctl_phy->dx[i].bdlr3);
366 for (j = 0; j < 4; j++)
367 val += para->dx_read_delays[i][j] << (j * 8);
368 writel(val, &mctl_phy->dx[i].bdlr3);
370 val = readl(&mctl_phy->dx[i].bdlr4);
371 for (j = 0; j < 4; j++)
372 val += para->dx_read_delays[i][j + 4] << (j * 8);
373 writel(val, &mctl_phy->dx[i].bdlr4);
375 val = readl(&mctl_phy->dx[i].bdlr5);
376 for (j = 0; j < 4; j++)
377 val += para->dx_read_delays[i][j + 8] << (j * 8);
378 writel(val, &mctl_phy->dx[i].bdlr5);
380 val = readl(&mctl_phy->dx[i].bdlr6);
381 val += (para->dx_read_delays[i][12] << 8) |
382 (para->dx_read_delays[i][13] << 16);
383 writel(val, &mctl_phy->dx[i].bdlr6);
385 setbits_le32(&mctl_phy->pgcr[0], BIT(26));
388 if (para->type != SUNXI_DRAM_TYPE_LPDDR3)
391 for (i = 1; i < 14; i++) {
392 val = readl(&mctl_phy->acbdlr[i]);
394 writel(val, &mctl_phy->acbdlr[i]);
398 static void mctl_channel_init(struct dram_para *para)
400 struct sunxi_mctl_com_reg * const mctl_com =
401 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
402 struct sunxi_mctl_ctl_reg * const mctl_ctl =
403 (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE;
404 struct sunxi_mctl_phy_reg * const mctl_phy =
405 (struct sunxi_mctl_phy_reg *)SUNXI_DRAM_PHY0_BASE;
409 setbits_le32(&mctl_ctl->dfiupd[0], BIT(31) | BIT(30));
410 setbits_le32(&mctl_ctl->zqctl[0], BIT(31) | BIT(30));
411 writel(0x2f05, &mctl_ctl->sched[0]);
412 setbits_le32(&mctl_ctl->rfshctl3, BIT(0));
413 setbits_le32(&mctl_ctl->dfimisc, BIT(0));
414 setbits_le32(&mctl_ctl->unk_0x00c, BIT(8));
415 clrsetbits_le32(&mctl_phy->pgcr[1], 0x180, 0xc0);
416 /* TODO: non-LPDDR3 types */
417 clrsetbits_le32(&mctl_phy->pgcr[2], GENMASK(17, 0), ns_to_t(7800));
418 clrbits_le32(&mctl_phy->pgcr[6], BIT(0));
419 clrsetbits_le32(&mctl_phy->dxccr, 0xee0, 0x220);
420 /* TODO: VT compensation */
421 clrsetbits_le32(&mctl_phy->dsgcr, BIT(0), 0x440060);
422 clrbits_le32(&mctl_phy->vtcr[1], BIT(1));
424 for (i = 0; i < 4; i++)
425 clrsetbits_le32(&mctl_phy->dx[i].gcr[0], 0xe00, 0x800);
426 for (i = 0; i < 4; i++)
427 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, 0x5555);
428 for (i = 0; i < 4; i++)
429 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, 0x1010);
433 if (para->ranks == 2)
434 setbits_le32(&mctl_phy->dtcr[1], 0x30000);
436 clrsetbits_le32(&mctl_phy->dtcr[1], 0x30000, 0x10000);
438 if (sunxi_dram_is_lpddr(para->type))
439 clrbits_le32(&mctl_phy->dtcr[1], BIT(1));
440 if (para->ranks == 2) {
441 writel(0x00010001, &mctl_phy->rankidr);
442 writel(0x20000, &mctl_phy->odtcr);
444 writel(0x0, &mctl_phy->rankidr);
445 writel(0x10000, &mctl_phy->odtcr);
448 /* set bits [3:0] to 1? 0 not valid in ZynqMP d/s */
449 if (para->type == SUNXI_DRAM_TYPE_LPDDR3)
450 clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000040);
452 clrsetbits_le32(&mctl_phy->dtcr[0], 0xF0000000, 0x10000000);
453 if (para->clk <= 792) {
454 if (para->clk <= 672) {
455 if (para->clk <= 600)
465 /* FIXME: NOT REVIEWED YET */
466 clrsetbits_le32(&mctl_phy->zq[0].zqcr, 0x700, val);
467 clrsetbits_le32(&mctl_phy->zq[0].zqpr[0], 0xff,
468 CONFIG_DRAM_ZQ & 0xff);
469 clrbits_le32(&mctl_phy->zq[0].zqor[0], 0xfffff);
470 setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ >> 8) & 0xff);
471 setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xf00) - 0x100);
472 setbits_le32(&mctl_phy->zq[0].zqor[0], (CONFIG_DRAM_ZQ & 0xff00) << 4);
473 clrbits_le32(&mctl_phy->zq[1].zqpr[0], 0xfffff);
474 setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ >> 16) & 0xff);
475 setbits_le32(&mctl_phy->zq[1].zqpr[0], ((CONFIG_DRAM_ZQ >> 8) & 0xf00) - 0x100);
476 setbits_le32(&mctl_phy->zq[1].zqpr[0], (CONFIG_DRAM_ZQ & 0xff0000) >> 4);
477 if (para->type == SUNXI_DRAM_TYPE_LPDDR3) {
478 for (i = 1; i < 14; i++)
479 writel(0x06060606, &mctl_phy->acbdlr[i]);
482 val = PIR_ZCAL | PIR_DCAL | PIR_PHYRST | PIR_DRAMINIT | PIR_QSGATE |
483 PIR_RDDSKW | PIR_WRDSKW | PIR_RDEYE | PIR_WREYE;
484 if (para->type == SUNXI_DRAM_TYPE_DDR3)
485 val |= PIR_DRAMRST | PIR_WL;
486 mctl_phy_pir_init(val);
488 /* TODO: DDR4 types ? */
489 for (i = 0; i < 4; i++)
490 writel(0x00000909, &mctl_phy->dx[i].gcr[5]);
492 for (i = 0; i < 4; i++) {
493 if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
497 clrsetbits_le32(&mctl_phy->dx[i].gcr[2], 0xffff, val);
499 if (IS_ENABLED(CONFIG_DRAM_ODT_EN))
503 clrsetbits_le32(&mctl_phy->dx[i].gcr[3], 0x3030, val);
506 mctl_bit_delay_set(para);
509 setbits_le32(&mctl_phy->pgcr[6], BIT(0));
510 clrbits_le32(&mctl_phy->pgcr[6], 0xfff8);
511 for (i = 0; i < 4; i++)
512 clrbits_le32(&mctl_phy->dx[i].gcr[3], ~0x3ffff);
515 if (readl(&mctl_phy->pgsr[0]) & 0x400000)
518 * Detect single rank.
519 * TODO: also detect half DQ.
521 if ((readl(&mctl_phy->dx[0].rsr[0]) & 0x3) == 2 &&
522 (readl(&mctl_phy->dx[1].rsr[0]) & 0x3) == 2 &&
523 (readl(&mctl_phy->dx[2].rsr[0]) & 0x3) == 2 &&
524 (readl(&mctl_phy->dx[3].rsr[0]) & 0x3) == 2) {
526 /* Restart DRAM initialization from scratch. */
527 mctl_core_init(para);
531 panic("This DRAM setup is currently not supported.\n");
535 if (readl(&mctl_phy->pgsr[0]) & 0xff00000) {
536 /* Oops! There's something wrong! */
537 debug("PLL = %x\n", readl(0x3001010));
538 debug("DRAM PHY PGSR0 = %x\n", readl(&mctl_phy->pgsr[0]));
539 for (i = 0; i < 4; i++)
540 debug("DRAM PHY DX%dRSR0 = %x\n", i, readl(&mctl_phy->dx[i].rsr[0]));
541 panic("Error while initializing DRAM PHY!\n");
544 if (sunxi_dram_is_lpddr(para->type))
545 clrsetbits_le32(&mctl_phy->dsgcr, 0xc0, 0x40);
546 clrbits_le32(&mctl_phy->pgcr[1], 0x40);
547 clrbits_le32(&mctl_ctl->dfimisc, BIT(0));
548 writel(1, &mctl_ctl->swctl);
549 mctl_await_completion(&mctl_ctl->swstat, 1, 1);
550 clrbits_le32(&mctl_ctl->rfshctl3, BIT(0));
552 setbits_le32(&mctl_com->unk_0x014, BIT(31));
553 writel(0xffffffff, &mctl_com->maer0);
554 writel(0x7ff, &mctl_com->maer1);
555 writel(0xffff, &mctl_com->maer2);
558 static void mctl_auto_detect_dram_size(struct dram_para *para)
560 /* TODO: non-LPDDR3, half DQ */
562 * Detect rank number by the code in mctl_channel_init. Furtherly
563 * when DQ detection is available it will also be executed there.
565 mctl_core_init(para);
567 /* detect row address bits */
570 mctl_core_init(para);
572 for (para->rows = 13; para->rows < 18; para->rows++) {
573 /* 8 banks, 8 bit per byte and 32 bit width */
574 if (mctl_mem_matches((1 << (para->rows + para->cols + 5))))
578 /* detect column address bits */
580 mctl_core_init(para);
582 for (para->cols = 8; para->cols < 11; para->cols++) {
583 /* 8 bits per byte and 32 bit width */
584 if (mctl_mem_matches(1 << (para->cols + 2)))
589 unsigned long mctl_calc_size(struct dram_para *para)
591 /* TODO: non-LPDDR3, half DQ */
593 /* 8 banks, 32-bit (4 byte) data width */
594 return (1ULL << (para->cols + para->rows + 3)) * 4 * para->ranks;
597 #define SUN50I_H6_DX_WRITE_DELAYS \
598 {{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
599 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, \
600 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 4, 4, 0 }, \
601 { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }}
602 #define SUN50I_H6_DX_READ_DELAYS \
603 {{ 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
604 { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
605 { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }, \
606 { 4, 4, 4, 4, 4, 4, 4, 4, 4, 0, 0, 0, 0, 0 }}
608 unsigned long sunxi_dram_init(void)
610 struct sunxi_mctl_com_reg * const mctl_com =
611 (struct sunxi_mctl_com_reg *)SUNXI_DRAM_COM_BASE;
612 struct dram_para para = {
613 .clk = CONFIG_DRAM_CLK,
617 #ifdef CONFIG_SUNXI_DRAM_H6_LPDDR3
618 .type = SUNXI_DRAM_TYPE_LPDDR3,
619 .dx_read_delays = SUN50I_H6_DX_READ_DELAYS,
620 .dx_write_delays = SUN50I_H6_DX_WRITE_DELAYS,
621 #elif defined(CONFIG_SUNXI_DRAM_H6_DDR3_1333)
622 .type = SUNXI_DRAM_TYPE_DDR3,
623 .dx_read_delays = SUN50I_H6_DX_READ_DELAYS,
624 .dx_write_delays = SUN50I_H6_DX_WRITE_DELAYS,
630 /* RES_CAL_CTRL_REG in BSP U-boot*/
631 setbits_le32(0x7010310, BIT(8));
632 clrbits_le32(0x7010318, 0x3f);
634 mctl_auto_detect_dram_size(¶);
636 mctl_core_init(¶);
638 size = mctl_calc_size(¶);
640 clrsetbits_le32(&mctl_com->cr, 0xf0, (size >> (10 + 10 + 4)) & 0xf0);
642 mctl_set_master_priority();