1 // SPDX-License-Identifier: GPL-2.0+
3 * sun6i specific clock code
5 * (C) Copyright 2007-2012
6 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
7 * Tom Cubie <tangliang@allwinnertech.com>
9 * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
14 #include <asm/arch/clock.h>
15 #include <asm/arch/prcm.h>
16 #include <asm/arch/sys_proto.h>
17 #include <linux/delay.h>
19 #ifdef CONFIG_SPL_BUILD
20 void clock_init_safe(void)
22 struct sunxi_ccm_reg * const ccm =
23 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
25 #if !defined(CONFIG_MACH_SUNXI_H3_H5) && !defined(CONFIG_MACH_SUN50I)
26 struct sunxi_prcm_reg * const prcm =
27 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
29 /* Set PLL ldo voltage without this PLL6 does not work properly */
30 clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
31 PRCM_PLL_CTRL_LDO_KEY);
32 clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
33 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
34 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
35 clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
38 #if defined(CONFIG_MACH_SUN8I_R40) || defined(CONFIG_MACH_SUN50I)
39 /* Set PLL lock enable bits and switch to old lock mode */
40 writel(GENMASK(12, 0), &ccm->pll_lock_ctrl);
43 clock_set_pll1(408000000);
45 writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
46 while (!(readl(&ccm->pll6_cfg) & CCM_PLL6_CTRL_LOCK))
49 writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
51 writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
52 if (IS_ENABLED(CONFIG_MACH_SUN6I))
53 writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
55 #if defined(CONFIG_MACH_SUN8I_R40) && defined(CONFIG_SUNXI_AHCI)
56 setbits_le32(&ccm->sata_pll_cfg, CCM_SATA_PLL_DEFAULT);
57 setbits_le32(&ccm->ahb_reset0_cfg, 0x1 << AHB_GATE_OFFSET_SATA);
58 setbits_le32(&ccm->ahb_gate0, 0x1 << AHB_GATE_OFFSET_SATA);
59 setbits_le32(&ccm->sata_clk_cfg, CCM_SATA_CTRL_ENABLE);
64 void clock_init_sec(void)
66 #ifdef CONFIG_MACH_SUNXI_H3_H5
67 struct sunxi_ccm_reg * const ccm =
68 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
69 struct sunxi_prcm_reg * const prcm =
70 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
72 setbits_le32(&ccm->ccu_sec_switch,
73 CCM_SEC_SWITCH_MBUS_NONSEC |
74 CCM_SEC_SWITCH_BUS_NONSEC |
75 CCM_SEC_SWITCH_PLL_NONSEC);
76 setbits_le32(&prcm->prcm_sec_switch,
77 PRCM_SEC_SWITCH_APB0_CLK_NONSEC |
78 PRCM_SEC_SWITCH_PLL_CFG_NONSEC |
79 PRCM_SEC_SWITCH_PWR_GATE_NONSEC);
83 void clock_init_uart(void)
85 #if CONFIG_CONS_INDEX < 5
86 struct sunxi_ccm_reg *const ccm =
87 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
89 /* uart clock source is apb2 */
90 writel(APB2_CLK_SRC_OSC24M|
95 /* open the clock for uart */
96 setbits_le32(&ccm->apb2_gate,
97 CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
98 CONFIG_CONS_INDEX - 1));
100 /* deassert uart reset */
101 setbits_le32(&ccm->apb2_reset_cfg,
102 1 << (APB2_RESET_UART_SHIFT +
103 CONFIG_CONS_INDEX - 1));
105 /* enable R_PIO and R_UART clocks, and de-assert resets */
106 prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
110 #ifdef CONFIG_SPL_BUILD
111 void clock_set_pll1(unsigned int clk)
113 struct sunxi_ccm_reg * const ccm =
114 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
119 if (clk > 1152000000) {
121 } else if (clk > 768000000) {
126 /* Switch to 24MHz clock while changing PLL1 */
127 writel(AXI_DIV_3 << AXI_DIV_SHIFT |
128 ATB_DIV_2 << ATB_DIV_SHIFT |
129 CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
133 * sun6i: PLL1 rate = ((24000000 * n * k) >> 0) / m (p is ignored)
134 * sun8i: PLL1 rate = ((24000000 * n * k) >> p) / m
136 writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_P(p) |
137 CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
138 CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
141 /* Switch CPU to PLL1 */
142 writel(AXI_DIV_3 << AXI_DIV_SHIFT |
143 ATB_DIV_2 << ATB_DIV_SHIFT |
144 CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
149 void clock_set_pll3(unsigned int clk)
151 struct sunxi_ccm_reg * const ccm =
152 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
153 #ifdef CONFIG_SUNXI_DE2
154 const int m = 4; /* 6 MHz steps to allow higher frequency for DE2 */
156 const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
160 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
164 /* PLL3 rate = 24000000 * n / m */
165 writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
166 CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
170 #ifdef CONFIG_SUNXI_DE2
171 void clock_set_pll3_factors(int m, int n)
173 struct sunxi_ccm_reg * const ccm =
174 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
176 /* PLL3 rate = 24000000 * n / m */
177 writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
178 CCM_PLL3_CTRL_N(n) | CCM_PLL3_CTRL_M(m),
181 while (!(readl(&ccm->pll3_cfg) & CCM_PLL3_CTRL_LOCK))
186 void clock_set_pll5(unsigned int clk, bool sigma_delta_enable)
188 struct sunxi_ccm_reg * const ccm =
189 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
190 const int max_n = 32;
193 #ifdef CONFIG_MACH_SUNXI_H3_H5
194 clrsetbits_le32(&ccm->pll5_tuning_cfg, CCM_PLL5_TUN_LOCK_TIME_MASK |
195 CCM_PLL5_TUN_INIT_FREQ_MASK,
196 CCM_PLL5_TUN_LOCK_TIME(2) | CCM_PLL5_TUN_INIT_FREQ(16));
199 if (sigma_delta_enable)
200 writel(CCM_PLL5_PATTERN, &ccm->pll5_pattern_cfg);
202 /* PLL5 rate = 24000000 * n * k / m */
203 if (clk > 24000000 * k * max_n / m) {
205 if (clk > 24000000 * k * max_n / m)
208 writel(CCM_PLL5_CTRL_EN |
209 (sigma_delta_enable ? CCM_PLL5_CTRL_SIGMA_DELTA_EN : 0) |
211 CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
212 CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
217 #ifdef CONFIG_MACH_SUN6I
218 void clock_set_mipi_pll(unsigned int clk)
220 struct sunxi_ccm_reg * const ccm =
221 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
222 unsigned int k, m, n, value, diff;
223 unsigned best_k = 0, best_m = 0, best_n = 0, best_diff = 0xffffffff;
224 unsigned int src = clock_get_pll3();
226 /* All calculations are in KHz to avoid overflows */
230 /* Pick the closest lower clock */
231 for (k = 1; k <= 4; k++) {
232 for (m = 1; m <= 16; m++) {
233 for (n = 1; n <= 16; n++) {
234 value = src * n * k / m;
239 if (diff < best_diff) {
252 writel(CCM_MIPI_PLL_CTRL_EN | CCM_MIPI_PLL_CTRL_LDO_EN |
253 CCM_MIPI_PLL_CTRL_N(best_n) | CCM_MIPI_PLL_CTRL_K(best_k) |
254 CCM_MIPI_PLL_CTRL_M(best_m), &ccm->mipi_pll_cfg);
258 #ifdef CONFIG_SUNXI_DE2
259 void clock_set_pll10(unsigned int clk)
261 struct sunxi_ccm_reg * const ccm =
262 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
263 const int m = 2; /* 12 MHz steps */
266 clrbits_le32(&ccm->pll10_cfg, CCM_PLL10_CTRL_EN);
270 /* PLL10 rate = 24000000 * n / m */
271 writel(CCM_PLL10_CTRL_EN | CCM_PLL10_CTRL_INTEGER_MODE |
272 CCM_PLL10_CTRL_N(clk / (24000000 / m)) | CCM_PLL10_CTRL_M(m),
275 while (!(readl(&ccm->pll10_cfg) & CCM_PLL10_CTRL_LOCK))
280 #if defined(CONFIG_MACH_SUN8I_A33) || \
281 defined(CONFIG_MACH_SUN8I_R40) || \
282 defined(CONFIG_MACH_SUN50I)
283 void clock_set_pll11(unsigned int clk, bool sigma_delta_enable)
285 struct sunxi_ccm_reg * const ccm =
286 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
288 if (sigma_delta_enable)
289 writel(CCM_PLL11_PATTERN, &ccm->pll11_pattern_cfg0);
291 writel(CCM_PLL11_CTRL_EN | CCM_PLL11_CTRL_UPD |
292 (sigma_delta_enable ? CCM_PLL11_CTRL_SIGMA_DELTA_EN : 0) |
293 CCM_PLL11_CTRL_N(clk / 24000000), &ccm->pll11_cfg);
295 while (readl(&ccm->pll11_cfg) & CCM_PLL11_CTRL_UPD)
300 unsigned int clock_get_pll3(void)
302 struct sunxi_ccm_reg *const ccm =
303 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
304 uint32_t rval = readl(&ccm->pll3_cfg);
305 int n = ((rval & CCM_PLL3_CTRL_N_MASK) >> CCM_PLL3_CTRL_N_SHIFT) + 1;
306 int m = ((rval & CCM_PLL3_CTRL_M_MASK) >> CCM_PLL3_CTRL_M_SHIFT) + 1;
308 /* Multiply by 1000 after dividing by m to avoid integer overflows */
309 return (24000 * n / m) * 1000;
312 unsigned int clock_get_pll6(void)
314 struct sunxi_ccm_reg *const ccm =
315 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
316 uint32_t rval = readl(&ccm->pll6_cfg);
317 int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
318 int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
319 return 24000000 * n * k / 2;
322 unsigned int clock_get_mipi_pll(void)
324 struct sunxi_ccm_reg *const ccm =
325 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
326 uint32_t rval = readl(&ccm->mipi_pll_cfg);
327 unsigned int n = ((rval & CCM_MIPI_PLL_CTRL_N_MASK) >> CCM_MIPI_PLL_CTRL_N_SHIFT) + 1;
328 unsigned int k = ((rval & CCM_MIPI_PLL_CTRL_K_MASK) >> CCM_MIPI_PLL_CTRL_K_SHIFT) + 1;
329 unsigned int m = ((rval & CCM_MIPI_PLL_CTRL_M_MASK) >> CCM_MIPI_PLL_CTRL_M_SHIFT) + 1;
330 unsigned int src = clock_get_pll3();
332 /* Multiply by 1000 after dividing by m to avoid integer overflows */
333 return ((src / 1000) * n * k / m) * 1000;
336 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
338 int pll = clock_get_pll6() * 2;
341 while ((pll / div) > hz)
344 writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),