4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
33 config DRAM_SUN8I_A83T
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
46 bool "Allwinner sun6i internal P2WI controller"
48 If you say yes to this option, support will be included for the
49 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
51 The P2WI looks like an SMBus controller (which supports only byte
52 accesses), except that it only supports one slave device.
53 This interface is used to connect to specific PMIC devices (like the
59 Support for the PRCM (Power/Reset/Clock Management) unit available
63 bool "Sunxi AXP PMIC bus access helpers"
65 Select this PMIC bus access helpers for Sunxi platform PRCM or other
66 AXP family PMIC devices.
69 bool "Allwinner sunXi Reduced Serial Bus Driver"
71 Say y here to enable support for Allwinner's Reduced Serial Bus
72 (RSB) support. This controller is responsible for communicating
73 with various RSB based devices, such as AXP223, AXP8XX PMICs,
76 config SUNXI_HIGH_SRAM
80 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
81 with the first SRAM region being located at address 0.
82 Some newer SoCs map the boot ROM at address 0 instead and move the
83 SRAM to 64KB, just behind the mask ROM.
84 Chips using the latter setup are supposed to select this option to
85 adjust the addresses accordingly.
87 # Note only one of these may be selected at a time! But hidden choices are
88 # not supported by Kconfig
89 config SUNXI_GEN_SUN4I
92 Select this for sunxi SoCs which have resets and clocks set up
93 as the original A10 (mach-sun4i).
95 config SUNXI_GEN_SUN6I
98 Select this for sunxi SoCs which have sun6i like periphery, like
99 separate ahb reset control registers, custom pmic bus, new style
105 Select this for sunxi SoCs which uses a DRAM controller like the
106 DesignWare controller used in H3, mainly SoCs after H3, which do
107 not have official open-source DRAM initialization code, but can
108 use modified H3 DRAM initialization code.
111 config SUNXI_DRAM_DW_16BIT
114 Select this for sunxi SoCs with DesignWare DRAM controller and
115 have only 16-bit memory buswidth.
117 config SUNXI_DRAM_DW_32BIT
120 Select this for sunxi SoCs with DesignWare DRAM controller with
121 32-bit memory buswidth.
124 config MACH_SUNXI_H3_H5
129 select SUNXI_DRAM_DW_32BIT
130 select SUNXI_GEN_SUN6I
134 prompt "Sunxi SoC Variant"
138 bool "sun4i (Allwinner A10)"
140 select ARM_CORTEX_CPU_IS_UP
142 select SUNXI_GEN_SUN4I
146 bool "sun5i (Allwinner A13)"
148 select ARM_CORTEX_CPU_IS_UP
150 select SUNXI_GEN_SUN4I
152 imply CONS_INDEX_2 if !DM_SERIAL
155 bool "sun6i (Allwinner A31)"
157 select CPU_V7_HAS_NONSEC
158 select CPU_V7_HAS_VIRT
159 select ARCH_SUPPORT_PSCI
163 select SUNXI_GEN_SUN6I
165 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
168 bool "sun7i (Allwinner A20)"
170 select CPU_V7_HAS_NONSEC
171 select CPU_V7_HAS_VIRT
172 select ARCH_SUPPORT_PSCI
174 select SUNXI_GEN_SUN4I
176 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
178 config MACH_SUN8I_A23
179 bool "sun8i (Allwinner A23)"
181 select CPU_V7_HAS_NONSEC
182 select CPU_V7_HAS_VIRT
183 select ARCH_SUPPORT_PSCI
184 select DRAM_SUN8I_A23
185 select SUNXI_GEN_SUN6I
187 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
188 imply CONS_INDEX_5 if !DM_SERIAL
190 config MACH_SUN8I_A33
191 bool "sun8i (Allwinner A33)"
193 select CPU_V7_HAS_NONSEC
194 select CPU_V7_HAS_VIRT
195 select ARCH_SUPPORT_PSCI
196 select DRAM_SUN8I_A33
197 select SUNXI_GEN_SUN6I
199 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
200 imply CONS_INDEX_5 if !DM_SERIAL
202 config MACH_SUN8I_A83T
203 bool "sun8i (Allwinner A83T)"
205 select DRAM_SUN8I_A83T
206 select SUNXI_GEN_SUN6I
207 select MMC_SUNXI_HAS_NEW_MODE
211 bool "sun8i (Allwinner H3)"
213 select CPU_V7_HAS_NONSEC
214 select CPU_V7_HAS_VIRT
215 select ARCH_SUPPORT_PSCI
216 select MACH_SUNXI_H3_H5
217 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
219 config MACH_SUN8I_R40
220 bool "sun8i (Allwinner R40)"
222 select CPU_V7_HAS_NONSEC
223 select CPU_V7_HAS_VIRT
224 select ARCH_SUPPORT_PSCI
225 select SUNXI_GEN_SUN6I
228 select SUNXI_DRAM_DW_32BIT
230 config MACH_SUN8I_V3S
231 bool "sun8i (Allwinner V3s)"
233 select CPU_V7_HAS_NONSEC
234 select CPU_V7_HAS_VIRT
235 select ARCH_SUPPORT_PSCI
236 select SUNXI_GEN_SUN6I
238 select SUNXI_DRAM_DW_16BIT
240 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
243 bool "sun9i (Allwinner A80)"
247 select SUNXI_HIGH_SRAM
248 select SUNXI_GEN_SUN6I
253 bool "sun50i (Allwinner A64)"
257 select SUNXI_GEN_SUN6I
258 select SUNXI_HIGH_SRAM
261 select SUNXI_DRAM_DW_32BIT
265 config MACH_SUN50I_H5
266 bool "sun50i (Allwinner H5)"
268 select MACH_SUNXI_H3_H5
269 select SUNXI_HIGH_SRAM
275 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
280 default y if MACH_SUN8I_A23
281 default y if MACH_SUN8I_A33
282 default y if MACH_SUN8I_A83T
283 default y if MACH_SUNXI_H3_H5
284 default y if MACH_SUN8I_R40
285 default y if MACH_SUN8I_V3S
287 config RESERVE_ALLWINNER_BOOT0_HEADER
288 bool "reserve space for Allwinner boot0 header"
289 select ENABLE_ARM_SOC_BOOT0_HOOK
291 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
292 filled with magic values post build. The Allwinner provided boot0
293 blob relies on this information to load and execute U-Boot.
294 Only needed on 64-bit Allwinner boards so far when using boot0.
296 config ARM_BOOT_HOOK_RMR
300 select ENABLE_ARM_SOC_BOOT0_HOOK
302 Insert some ARM32 code at the very beginning of the U-Boot binary
303 which uses an RMR register write to bring the core into AArch64 mode.
304 The very first instruction acts as a switch, since it's carefully
305 chosen to be a NOP in one mode and a branch in the other, so the
306 code would only be executed if not already in AArch64.
307 This allows both the SPL and the U-Boot proper to be entered in
308 either mode and switch to AArch64 if needed.
311 config SUNXI_DRAM_DDR3
314 config SUNXI_DRAM_DDR2
317 config SUNXI_DRAM_LPDDR3
321 prompt "DRAM Type and Timing"
322 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
323 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
325 config SUNXI_DRAM_DDR3_1333
327 select SUNXI_DRAM_DDR3
328 depends on !MACH_SUN8I_V3S
330 This option is the original only supported memory type, which suits
331 many H3/H5/A64 boards available now.
333 config SUNXI_DRAM_LPDDR3_STOCK
334 bool "LPDDR3 with Allwinner stock configuration"
335 select SUNXI_DRAM_LPDDR3
337 This option is the LPDDR3 timing used by the stock boot0 by
340 config SUNXI_DRAM_DDR2_V3S
341 bool "DDR2 found in V3s chip"
342 select SUNXI_DRAM_DDR2
343 depends on MACH_SUN8I_V3S
345 This option is only for the DDR2 memory chip which is co-packaged in
352 int "sunxi dram type"
353 depends on MACH_SUN8I_A83T
356 Set the dram type, 3: DDR3, 7: LPDDR3
359 int "sunxi dram clock speed"
360 default 792 if MACH_SUN9I
361 default 648 if MACH_SUN8I_R40
362 default 312 if MACH_SUN6I || MACH_SUN8I
363 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
365 default 672 if MACH_SUN50I
367 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
368 must be a multiple of 24. For the sun9i (A80), the tested values
369 (for DDR3-1600) are 312 to 792.
371 if MACH_SUN5I || MACH_SUN7I
373 int "sunxi mbus clock speed"
376 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
381 int "sunxi dram zq value"
382 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
383 default 127 if MACH_SUN7I
384 default 14779 if MACH_SUN8I_V3S
385 default 3881979 if MACH_SUN8I_R40
386 default 4145117 if MACH_SUN9I
387 default 3881915 if MACH_SUN50I
389 Set the dram zq value.
392 bool "sunxi dram odt enable"
393 default n if !MACH_SUN8I_A23
394 default y if MACH_SUN8I_A23
395 default y if MACH_SUN8I_R40
396 default y if MACH_SUN50I
398 Select this to enable dram odt (on die termination).
400 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
402 int "sunxi dram emr1 value"
403 default 0 if MACH_SUN4I
404 default 4 if MACH_SUN5I || MACH_SUN7I
406 Set the dram controller emr1 value.
409 hex "sunxi dram tpr3 value"
412 Set the dram controller tpr3 parameter. This parameter configures
413 the delay on the command lane and also phase shifts, which are
414 applied for sampling incoming read data. The default value 0
415 means that no phase/delay adjustments are necessary. Properly
416 configuring this parameter increases reliability at high DRAM
419 config DRAM_DQS_GATING_DELAY
420 hex "sunxi dram dqs_gating_delay value"
423 Set the dram controller dqs_gating_delay parmeter. Each byte
424 encodes the DQS gating delay for each byte lane. The delay
425 granularity is 1/4 cycle. For example, the value 0x05060606
426 means that the delay is 5 quarter-cycles for one lane (1.25
427 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
428 The default value 0 means autodetection. The results of hardware
429 autodetection are not very reliable and depend on the chip
430 temperature (sometimes producing different results on cold start
431 and warm reboot). But the accuracy of hardware autodetection
432 is usually good enough, unless running at really high DRAM
433 clocks speeds (up to 600MHz). If unsure, keep as 0.
436 prompt "sunxi dram timings"
437 default DRAM_TIMINGS_VENDOR_MAGIC
439 Select the timings of the DDR3 chips.
441 config DRAM_TIMINGS_VENDOR_MAGIC
442 bool "Magic vendor timings from Android"
444 The same DRAM timings as in the Allwinner boot0 bootloader.
446 config DRAM_TIMINGS_DDR3_1066F_1333H
447 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
449 Use the timings of the standard JEDEC DDR3-1066F speed bin for
450 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
451 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
452 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
453 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
454 that down binning to DDR3-1066F is supported (because DDR3-1066F
455 uses a bit faster timings than DDR3-1333H).
457 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
458 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
460 Use the timings of the slowest possible JEDEC speed bin for the
461 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
462 DDR3-800E, DDR3-1066G or DDR3-1333J.
469 config DRAM_ODT_CORRECTION
470 int "sunxi dram odt correction value"
473 Set the dram odt correction value (range -255 - 255). In allwinner
474 fex files, this option is found in bits 8-15 of the u32 odt_en variable
475 in the [dram] section. When bit 31 of the odt_en variable is set
476 then the correction is negative. Usually the value for this is 0.
480 default 1008000000 if MACH_SUN4I
481 default 1008000000 if MACH_SUN5I
482 default 1008000000 if MACH_SUN6I
483 default 912000000 if MACH_SUN7I
484 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
485 default 1008000000 if MACH_SUN8I
486 default 1008000000 if MACH_SUN9I
488 config SYS_CONFIG_NAME
489 default "sun4i" if MACH_SUN4I
490 default "sun5i" if MACH_SUN5I
491 default "sun6i" if MACH_SUN6I
492 default "sun7i" if MACH_SUN7I
493 default "sun8i" if MACH_SUN8I
494 default "sun9i" if MACH_SUN9I
495 default "sun50i" if MACH_SUN50I
504 bool "UART0 on MicroSD breakout board"
507 Repurpose the SD card slot for getting access to the UART0 serial
508 console. Primarily useful only for low level u-boot debugging on
509 tablets, where normal UART0 is difficult to access and requires
510 device disassembly and/or soldering. As the SD card can't be used
511 at the same time, the system can be only booted in the FEL mode.
512 Only enable this if you really know what you are doing.
514 config OLD_SUNXI_KERNEL_COMPAT
515 bool "Enable workarounds for booting old kernels"
518 Set this to enable various workarounds for old kernels, this results in
519 sub-optimal settings for newer kernels, only enable if needed.
522 string "MAC power pin"
525 Set the pin used to power the MAC. This takes a string in the format
526 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
529 string "Card detect pin for mmc0"
530 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
533 Set the card detect pin for mmc0, leave empty to not use cd. This
534 takes a string in the format understood by sunxi_name_to_gpio, e.g.
535 PH1 for pin 1 of port H.
538 string "Card detect pin for mmc1"
541 See MMC0_CD_PIN help text.
544 string "Card detect pin for mmc2"
547 See MMC0_CD_PIN help text.
550 string "Card detect pin for mmc3"
553 See MMC0_CD_PIN help text.
556 string "Pins for mmc1"
559 Set the pins used for mmc1, when applicable. This takes a string in the
560 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
563 string "Pins for mmc2"
566 See MMC1_PINS help text.
569 string "Pins for mmc3"
572 See MMC1_PINS help text.
574 config MMC_SUNXI_SLOT_EXTRA
575 int "mmc extra slot number"
578 sunxi builds always enable mmc0, some boards also have a second sdcard
579 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
582 config INITIAL_USB_SCAN_DELAY
583 int "delay initial usb scan by x ms to allow builtin devices to init"
586 Some boards have on board usb devices which need longer than the
587 USB spec's 1 second to connect from board powerup. Set this config
588 option to a non 0 value to add an extra delay before the first usb
592 string "Vbus enable pin for usb0 (otg)"
595 Set the Vbus enable pin for usb0 (otg). This takes a string in the
596 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
599 string "Vbus detect pin for usb0 (otg)"
602 Set the Vbus detect pin for usb0 (otg). This takes a string in the
603 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
606 string "ID detect pin for usb0 (otg)"
609 Set the ID detect pin for usb0 (otg). This takes a string in the
610 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
613 string "Vbus enable pin for usb1 (ehci0)"
614 default "PH6" if MACH_SUN4I || MACH_SUN7I
615 default "PH27" if MACH_SUN6I
617 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
618 a string in the format understood by sunxi_name_to_gpio, e.g.
619 PH1 for pin 1 of port H.
622 string "Vbus enable pin for usb2 (ehci1)"
623 default "PH3" if MACH_SUN4I || MACH_SUN7I
624 default "PH24" if MACH_SUN6I
626 See USB1_VBUS_PIN help text.
629 string "Vbus enable pin for usb3 (ehci2)"
632 See USB1_VBUS_PIN help text.
635 bool "Enable I2C/TWI controller 0"
636 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
637 default n if MACH_SUN6I || MACH_SUN8I
640 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
641 its clock and setting up the bus. This is especially useful on devices
642 with slaves connected to the bus or with pins exposed through e.g. an
643 expansion port/header.
646 bool "Enable I2C/TWI controller 1"
650 See I2C0_ENABLE help text.
653 bool "Enable I2C/TWI controller 2"
657 See I2C0_ENABLE help text.
659 if MACH_SUN6I || MACH_SUN7I
661 bool "Enable I2C/TWI controller 3"
665 See I2C0_ENABLE help text.
670 bool "Enable the PRCM I2C/TWI controller"
671 # This is used for the pmic on H3
672 default y if SY8106A_POWER
675 Set this to y to enable the I2C controller which is part of the PRCM.
680 bool "Enable I2C/TWI controller 4"
684 See I2C0_ENABLE help text.
688 bool "Enable support for gpio-s on axp PMICs"
691 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
694 bool "Enable graphical uboot console on HDMI, LCD or VGA"
695 depends on !MACH_SUN8I_A83T
696 depends on !MACH_SUNXI_H3_H5
697 depends on !MACH_SUN8I_R40
698 depends on !MACH_SUN8I_V3S
699 depends on !MACH_SUN9I
700 depends on !MACH_SUN50I
702 imply VIDEO_DT_SIMPLEFB
705 Say Y here to add support for using a cfb console on the HDMI, LCD
706 or VGA output found on most sunxi devices. See doc/README.video for
707 info on how to select the video output and mode.
710 bool "HDMI output support"
711 depends on VIDEO_SUNXI && !MACH_SUN8I
714 Say Y here to add support for outputting video over HDMI.
717 bool "VGA output support"
718 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
721 Say Y here to add support for outputting video over VGA.
723 config VIDEO_VGA_VIA_LCD
724 bool "VGA via LCD controller support"
725 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
728 Say Y here to add support for external DACs connected to the parallel
729 LCD interface driving a VGA connector, such as found on the
732 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
733 bool "Force sync active high for VGA via LCD controller support"
734 depends on VIDEO_VGA_VIA_LCD
737 Say Y here if you've a board which uses opendrain drivers for the vga
738 hsync and vsync signals. Opendrain drivers cannot generate steep enough
739 positive edges for a stable video output, so on boards with opendrain
740 drivers the sync signals must always be active high.
742 config VIDEO_VGA_EXTERNAL_DAC_EN
743 string "LCD panel power enable pin"
744 depends on VIDEO_VGA_VIA_LCD
747 Set the enable pin for the external VGA DAC. This takes a string in the
748 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
750 config VIDEO_COMPOSITE
751 bool "Composite video output support"
752 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
755 Say Y here to add support for outputting composite video.
757 config VIDEO_LCD_MODE
758 string "LCD panel timing details"
759 depends on VIDEO_SUNXI
762 LCD panel timing details string, leave empty if there is no LCD panel.
763 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
764 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
765 Also see: http://linux-sunxi.org/LCD
767 config VIDEO_LCD_DCLK_PHASE
768 int "LCD panel display clock phase"
769 depends on VIDEO_SUNXI || DM_VIDEO
772 Select LCD panel display clock phase shift, range 0-3.
774 config VIDEO_LCD_POWER
775 string "LCD panel power enable pin"
776 depends on VIDEO_SUNXI
779 Set the power enable pin for the LCD panel. This takes a string in the
780 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
782 config VIDEO_LCD_RESET
783 string "LCD panel reset pin"
784 depends on VIDEO_SUNXI
787 Set the reset pin for the LCD panel. This takes a string in the format
788 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
790 config VIDEO_LCD_BL_EN
791 string "LCD panel backlight enable pin"
792 depends on VIDEO_SUNXI
795 Set the backlight enable pin for the LCD panel. This takes a string in the
796 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
799 config VIDEO_LCD_BL_PWM
800 string "LCD panel backlight pwm pin"
801 depends on VIDEO_SUNXI
804 Set the backlight pwm pin for the LCD panel. This takes a string in the
805 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
807 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
808 bool "LCD panel backlight pwm is inverted"
809 depends on VIDEO_SUNXI
812 Set this if the backlight pwm output is active low.
814 config VIDEO_LCD_PANEL_I2C
815 bool "LCD panel needs to be configured via i2c"
816 depends on VIDEO_SUNXI
820 Say y here if the LCD panel needs to be configured via i2c. This
821 will add a bitbang i2c controller using gpios to talk to the LCD.
823 config VIDEO_LCD_PANEL_I2C_SDA
824 string "LCD panel i2c interface SDA pin"
825 depends on VIDEO_LCD_PANEL_I2C
828 Set the SDA pin for the LCD i2c interface. This takes a string in the
829 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
831 config VIDEO_LCD_PANEL_I2C_SCL
832 string "LCD panel i2c interface SCL pin"
833 depends on VIDEO_LCD_PANEL_I2C
836 Set the SCL pin for the LCD i2c interface. This takes a string in the
837 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
840 # Note only one of these may be selected at a time! But hidden choices are
841 # not supported by Kconfig
842 config VIDEO_LCD_IF_PARALLEL
845 config VIDEO_LCD_IF_LVDS
853 bool "Display Engine 2 video driver"
857 imply VIDEO_DT_SIMPLEFB
860 Say y here if you want to build DE2 video driver which is present on
861 newer SoCs. Currently only HDMI output is supported.
865 prompt "LCD panel support"
866 depends on VIDEO_SUNXI
868 Select which type of LCD panel to support.
870 config VIDEO_LCD_PANEL_PARALLEL
871 bool "Generic parallel interface LCD panel"
872 select VIDEO_LCD_IF_PARALLEL
874 config VIDEO_LCD_PANEL_LVDS
875 bool "Generic lvds interface LCD panel"
876 select VIDEO_LCD_IF_LVDS
878 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
879 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
880 select VIDEO_LCD_SSD2828
881 select VIDEO_LCD_IF_PARALLEL
883 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
885 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
886 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
887 select VIDEO_LCD_ANX9804
888 select VIDEO_LCD_IF_PARALLEL
889 select VIDEO_LCD_PANEL_I2C
891 Select this for eDP LCD panels with 4 lanes running at 1.62G,
892 connected via an ANX9804 bridge chip.
894 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
895 bool "Hitachi tx18d42vm LCD panel"
896 select VIDEO_LCD_HITACHI_TX18D42VM
897 select VIDEO_LCD_IF_LVDS
899 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
901 config VIDEO_LCD_TL059WV5C0
902 bool "tl059wv5c0 LCD panel"
903 select VIDEO_LCD_PANEL_I2C
904 select VIDEO_LCD_IF_PARALLEL
906 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
907 Aigo M60/M608/M606 tablets.
912 string "SATA power pin"
915 Set the pins used to power the SATA. This takes a string in the
916 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
920 int "GMAC Transmit Clock Delay Chain"
923 Set the GMAC Transmit Clock Delay Chain value.
925 config SPL_STACK_R_ADDR
926 default 0x4fe00000 if MACH_SUN4I
927 default 0x4fe00000 if MACH_SUN5I
928 default 0x4fe00000 if MACH_SUN6I
929 default 0x4fe00000 if MACH_SUN7I
930 default 0x4fe00000 if MACH_SUN8I
931 default 0x2fe00000 if MACH_SUN9I
932 default 0x4fe00000 if MACH_SUN50I
935 bool "Support for SPI Flash on Allwinner SoCs in SPL"
936 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
938 Enable support for SPI Flash. This option allows SPL to read from
939 sunxi SPI Flash. It uses the same method as the boot ROM, so does
940 not need any extra configuration.