4 default " Allwinner Technology"
10 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
11 with the first SRAM region being located at address 0.
12 Some newer SoCs map the boot ROM at address 0 instead and move the
13 SRAM to 64KB, just behind the mask ROM.
14 Chips using the latter setup are supposed to select this option to
15 adjust the addresses accordingly.
17 # Note only one of these may be selected at a time! But hidden choices are
18 # not supported by Kconfig
19 config SUNXI_GEN_SUN4I
22 Select this for sunxi SoCs which have resets and clocks set up
23 as the original A10 (mach-sun4i).
25 config SUNXI_GEN_SUN6I
28 Select this for sunxi SoCs which have sun6i like periphery, like
29 separate ahb reset control registers, custom pmic bus, new style
35 Select this for sunxi SoCs which uses a DRAM controller like the
36 DesignWare controller used in H3, mainly SoCs after H3, which do
37 not have official open-source DRAM initialization code, but can
38 use modified H3 DRAM initialization code.
41 config SUNXI_DRAM_DW_16BIT
44 Select this for sunxi SoCs with DesignWare DRAM controller and
45 have only 16-bit memory buswidth.
47 config SUNXI_DRAM_DW_32BIT
50 Select this for sunxi SoCs with DesignWare DRAM controller with
51 32-bit memory buswidth.
54 config MACH_SUNXI_H3_H5
59 select SUNXI_DRAM_DW_32BIT
60 select SUNXI_GEN_SUN6I
64 prompt "Sunxi SoC Variant"
68 bool "sun4i (Allwinner A10)"
70 select ARM_CORTEX_CPU_IS_UP
71 select SUNXI_GEN_SUN4I
75 bool "sun5i (Allwinner A13)"
77 select ARM_CORTEX_CPU_IS_UP
78 select SUNXI_GEN_SUN4I
82 bool "sun6i (Allwinner A31)"
84 select CPU_V7_HAS_NONSEC
85 select CPU_V7_HAS_VIRT
86 select ARCH_SUPPORT_PSCI
87 select SUNXI_GEN_SUN6I
89 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
92 bool "sun7i (Allwinner A20)"
94 select CPU_V7_HAS_NONSEC
95 select CPU_V7_HAS_VIRT
96 select ARCH_SUPPORT_PSCI
97 select SUNXI_GEN_SUN4I
99 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
101 config MACH_SUN8I_A23
102 bool "sun8i (Allwinner A23)"
104 select CPU_V7_HAS_NONSEC
105 select CPU_V7_HAS_VIRT
106 select ARCH_SUPPORT_PSCI
107 select SUNXI_GEN_SUN6I
109 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
111 config MACH_SUN8I_A33
112 bool "sun8i (Allwinner A33)"
114 select CPU_V7_HAS_NONSEC
115 select CPU_V7_HAS_VIRT
116 select ARCH_SUPPORT_PSCI
117 select SUNXI_GEN_SUN6I
119 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
121 config MACH_SUN8I_A83T
122 bool "sun8i (Allwinner A83T)"
124 select SUNXI_GEN_SUN6I
128 bool "sun8i (Allwinner H3)"
130 select CPU_V7_HAS_NONSEC
131 select CPU_V7_HAS_VIRT
132 select ARCH_SUPPORT_PSCI
133 select MACH_SUNXI_H3_H5
134 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
136 config MACH_SUN8I_R40
137 bool "sun8i (Allwinner R40)"
139 select CPU_V7_HAS_NONSEC
140 select CPU_V7_HAS_VIRT
141 select ARCH_SUPPORT_PSCI
142 select SUNXI_GEN_SUN6I
145 select SUNXI_DRAM_DW_32BIT
147 config MACH_SUN8I_V3S
148 bool "sun8i (Allwinner V3s)"
150 select CPU_V7_HAS_NONSEC
151 select CPU_V7_HAS_VIRT
152 select ARCH_SUPPORT_PSCI
153 select SUNXI_GEN_SUN6I
155 select SUNXI_DRAM_DW_16BIT
157 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
160 bool "sun9i (Allwinner A80)"
162 select SUNXI_HIGH_SRAM
163 select SUNXI_GEN_SUN6I
167 bool "sun50i (Allwinner A64)"
171 select SUNXI_GEN_SUN6I
172 select SUNXI_HIGH_SRAM
175 select SUNXI_DRAM_DW_32BIT
179 config MACH_SUN50I_H5
180 bool "sun50i (Allwinner H5)"
182 select MACH_SUNXI_H3_H5
183 select SUNXI_HIGH_SRAM
189 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
192 default y if MACH_SUN8I_A23
193 default y if MACH_SUN8I_A33
194 default y if MACH_SUN8I_A83T
195 default y if MACH_SUNXI_H3_H5
196 default y if MACH_SUN8I_R40
197 default y if MACH_SUN8I_V3S
199 config RESERVE_ALLWINNER_BOOT0_HEADER
200 bool "reserve space for Allwinner boot0 header"
201 select ENABLE_ARM_SOC_BOOT0_HOOK
203 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
204 filled with magic values post build. The Allwinner provided boot0
205 blob relies on this information to load and execute U-Boot.
206 Only needed on 64-bit Allwinner boards so far when using boot0.
208 config ARM_BOOT_HOOK_RMR
212 select ENABLE_ARM_SOC_BOOT0_HOOK
214 Insert some ARM32 code at the very beginning of the U-Boot binary
215 which uses an RMR register write to bring the core into AArch64 mode.
216 The very first instruction acts as a switch, since it's carefully
217 chosen to be a NOP in one mode and a branch in the other, so the
218 code would only be executed if not already in AArch64.
219 This allows both the SPL and the U-Boot proper to be entered in
220 either mode and switch to AArch64 if needed.
223 config SUNXI_DRAM_DDR3
226 config SUNXI_DRAM_DDR2
229 config SUNXI_DRAM_LPDDR3
233 prompt "DRAM Type and Timing"
234 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
235 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
237 config SUNXI_DRAM_DDR3_1333
239 select SUNXI_DRAM_DDR3
240 depends on !MACH_SUN8I_V3S
242 This option is the original only supported memory type, which suits
243 many H3/H5/A64 boards available now.
245 config SUNXI_DRAM_DDR2_V3S
246 bool "DDR2 found in V3s chip"
247 select SUNXI_DRAM_DDR2
248 depends on MACH_SUN8I_V3S
250 This option is only for the DDR2 memory chip which is co-packaged in
257 int "sunxi dram type"
258 depends on MACH_SUN8I_A83T
261 Set the dram type, 3: DDR3, 7: LPDDR3
264 int "sunxi dram clock speed"
265 default 792 if MACH_SUN9I
266 default 648 if MACH_SUN8I_R40
267 default 312 if MACH_SUN6I || MACH_SUN8I
268 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
270 default 672 if MACH_SUN50I
272 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
273 must be a multiple of 24. For the sun9i (A80), the tested values
274 (for DDR3-1600) are 312 to 792.
276 if MACH_SUN5I || MACH_SUN7I
278 int "sunxi mbus clock speed"
281 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
286 int "sunxi dram zq value"
287 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
288 default 127 if MACH_SUN7I
289 default 14779 if MACH_SUN8I_V3S
290 default 3881979 if MACH_SUN8I_R40
291 default 4145117 if MACH_SUN9I
292 default 3881915 if MACH_SUN50I
294 Set the dram zq value.
297 bool "sunxi dram odt enable"
298 default n if !MACH_SUN8I_A23
299 default y if MACH_SUN8I_A23
300 default y if MACH_SUN8I_R40
301 default y if MACH_SUN50I
303 Select this to enable dram odt (on die termination).
305 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
307 int "sunxi dram emr1 value"
308 default 0 if MACH_SUN4I
309 default 4 if MACH_SUN5I || MACH_SUN7I
311 Set the dram controller emr1 value.
314 hex "sunxi dram tpr3 value"
317 Set the dram controller tpr3 parameter. This parameter configures
318 the delay on the command lane and also phase shifts, which are
319 applied for sampling incoming read data. The default value 0
320 means that no phase/delay adjustments are necessary. Properly
321 configuring this parameter increases reliability at high DRAM
324 config DRAM_DQS_GATING_DELAY
325 hex "sunxi dram dqs_gating_delay value"
328 Set the dram controller dqs_gating_delay parmeter. Each byte
329 encodes the DQS gating delay for each byte lane. The delay
330 granularity is 1/4 cycle. For example, the value 0x05060606
331 means that the delay is 5 quarter-cycles for one lane (1.25
332 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
333 The default value 0 means autodetection. The results of hardware
334 autodetection are not very reliable and depend on the chip
335 temperature (sometimes producing different results on cold start
336 and warm reboot). But the accuracy of hardware autodetection
337 is usually good enough, unless running at really high DRAM
338 clocks speeds (up to 600MHz). If unsure, keep as 0.
341 prompt "sunxi dram timings"
342 default DRAM_TIMINGS_VENDOR_MAGIC
344 Select the timings of the DDR3 chips.
346 config DRAM_TIMINGS_VENDOR_MAGIC
347 bool "Magic vendor timings from Android"
349 The same DRAM timings as in the Allwinner boot0 bootloader.
351 config DRAM_TIMINGS_DDR3_1066F_1333H
352 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
354 Use the timings of the standard JEDEC DDR3-1066F speed bin for
355 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
356 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
357 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
358 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
359 that down binning to DDR3-1066F is supported (because DDR3-1066F
360 uses a bit faster timings than DDR3-1333H).
362 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
363 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
365 Use the timings of the slowest possible JEDEC speed bin for the
366 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
367 DDR3-800E, DDR3-1066G or DDR3-1333J.
374 config DRAM_ODT_CORRECTION
375 int "sunxi dram odt correction value"
378 Set the dram odt correction value (range -255 - 255). In allwinner
379 fex files, this option is found in bits 8-15 of the u32 odt_en variable
380 in the [dram] section. When bit 31 of the odt_en variable is set
381 then the correction is negative. Usually the value for this is 0.
385 default 1008000000 if MACH_SUN4I
386 default 1008000000 if MACH_SUN5I
387 default 1008000000 if MACH_SUN6I
388 default 912000000 if MACH_SUN7I
389 default 1008000000 if MACH_SUN8I
390 default 1008000000 if MACH_SUN9I
391 default 816000000 if MACH_SUN50I
393 config SYS_CONFIG_NAME
394 default "sun4i" if MACH_SUN4I
395 default "sun5i" if MACH_SUN5I
396 default "sun6i" if MACH_SUN6I
397 default "sun7i" if MACH_SUN7I
398 default "sun8i" if MACH_SUN8I
399 default "sun9i" if MACH_SUN9I
400 default "sun50i" if MACH_SUN50I
409 bool "UART0 on MicroSD breakout board"
412 Repurpose the SD card slot for getting access to the UART0 serial
413 console. Primarily useful only for low level u-boot debugging on
414 tablets, where normal UART0 is difficult to access and requires
415 device disassembly and/or soldering. As the SD card can't be used
416 at the same time, the system can be only booted in the FEL mode.
417 Only enable this if you really know what you are doing.
419 config OLD_SUNXI_KERNEL_COMPAT
420 bool "Enable workarounds for booting old kernels"
423 Set this to enable various workarounds for old kernels, this results in
424 sub-optimal settings for newer kernels, only enable if needed.
427 string "MAC power pin"
430 Set the pin used to power the MAC. This takes a string in the format
431 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
434 string "Card detect pin for mmc0"
435 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
438 Set the card detect pin for mmc0, leave empty to not use cd. This
439 takes a string in the format understood by sunxi_name_to_gpio, e.g.
440 PH1 for pin 1 of port H.
443 string "Card detect pin for mmc1"
446 See MMC0_CD_PIN help text.
449 string "Card detect pin for mmc2"
452 See MMC0_CD_PIN help text.
455 string "Card detect pin for mmc3"
458 See MMC0_CD_PIN help text.
461 string "Pins for mmc1"
464 Set the pins used for mmc1, when applicable. This takes a string in the
465 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
468 string "Pins for mmc2"
471 See MMC1_PINS help text.
474 string "Pins for mmc3"
477 See MMC1_PINS help text.
479 config MMC_SUNXI_SLOT_EXTRA
480 int "mmc extra slot number"
483 sunxi builds always enable mmc0, some boards also have a second sdcard
484 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
487 config INITIAL_USB_SCAN_DELAY
488 int "delay initial usb scan by x ms to allow builtin devices to init"
491 Some boards have on board usb devices which need longer than the
492 USB spec's 1 second to connect from board powerup. Set this config
493 option to a non 0 value to add an extra delay before the first usb
497 string "Vbus enable pin for usb0 (otg)"
500 Set the Vbus enable pin for usb0 (otg). This takes a string in the
501 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
504 string "Vbus detect pin for usb0 (otg)"
507 Set the Vbus detect pin for usb0 (otg). This takes a string in the
508 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
511 string "ID detect pin for usb0 (otg)"
514 Set the ID detect pin for usb0 (otg). This takes a string in the
515 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
518 string "Vbus enable pin for usb1 (ehci0)"
519 default "PH6" if MACH_SUN4I || MACH_SUN7I
520 default "PH27" if MACH_SUN6I
522 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
523 a string in the format understood by sunxi_name_to_gpio, e.g.
524 PH1 for pin 1 of port H.
527 string "Vbus enable pin for usb2 (ehci1)"
528 default "PH3" if MACH_SUN4I || MACH_SUN7I
529 default "PH24" if MACH_SUN6I
531 See USB1_VBUS_PIN help text.
534 string "Vbus enable pin for usb3 (ehci2)"
537 See USB1_VBUS_PIN help text.
540 bool "Enable I2C/TWI controller 0"
541 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
542 default n if MACH_SUN6I || MACH_SUN8I
545 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
546 its clock and setting up the bus. This is especially useful on devices
547 with slaves connected to the bus or with pins exposed through e.g. an
548 expansion port/header.
551 bool "Enable I2C/TWI controller 1"
555 See I2C0_ENABLE help text.
558 bool "Enable I2C/TWI controller 2"
562 See I2C0_ENABLE help text.
564 if MACH_SUN6I || MACH_SUN7I
566 bool "Enable I2C/TWI controller 3"
570 See I2C0_ENABLE help text.
575 bool "Enable the PRCM I2C/TWI controller"
576 # This is used for the pmic on H3
577 default y if SY8106A_POWER
580 Set this to y to enable the I2C controller which is part of the PRCM.
585 bool "Enable I2C/TWI controller 4"
589 See I2C0_ENABLE help text.
593 bool "Enable support for gpio-s on axp PMICs"
596 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
599 bool "Enable graphical uboot console on HDMI, LCD or VGA"
600 depends on !MACH_SUN8I_A83T
601 depends on !MACH_SUNXI_H3_H5
602 depends on !MACH_SUN8I_R40
603 depends on !MACH_SUN8I_V3S
604 depends on !MACH_SUN9I
605 depends on !MACH_SUN50I
608 Say Y here to add support for using a cfb console on the HDMI, LCD
609 or VGA output found on most sunxi devices. See doc/README.video for
610 info on how to select the video output and mode.
613 bool "HDMI output support"
614 depends on VIDEO && !MACH_SUN8I
617 Say Y here to add support for outputting video over HDMI.
620 bool "VGA output support"
621 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
624 Say Y here to add support for outputting video over VGA.
626 config VIDEO_VGA_VIA_LCD
627 bool "VGA via LCD controller support"
628 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
631 Say Y here to add support for external DACs connected to the parallel
632 LCD interface driving a VGA connector, such as found on the
635 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
636 bool "Force sync active high for VGA via LCD controller support"
637 depends on VIDEO_VGA_VIA_LCD
640 Say Y here if you've a board which uses opendrain drivers for the vga
641 hsync and vsync signals. Opendrain drivers cannot generate steep enough
642 positive edges for a stable video output, so on boards with opendrain
643 drivers the sync signals must always be active high.
645 config VIDEO_VGA_EXTERNAL_DAC_EN
646 string "LCD panel power enable pin"
647 depends on VIDEO_VGA_VIA_LCD
650 Set the enable pin for the external VGA DAC. This takes a string in the
651 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
653 config VIDEO_COMPOSITE
654 bool "Composite video output support"
655 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
658 Say Y here to add support for outputting composite video.
660 config VIDEO_LCD_MODE
661 string "LCD panel timing details"
665 LCD panel timing details string, leave empty if there is no LCD panel.
666 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
667 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
668 Also see: http://linux-sunxi.org/LCD
670 config VIDEO_LCD_DCLK_PHASE
671 int "LCD panel display clock phase"
675 Select LCD panel display clock phase shift, range 0-3.
677 config VIDEO_LCD_POWER
678 string "LCD panel power enable pin"
682 Set the power enable pin for the LCD panel. This takes a string in the
683 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
685 config VIDEO_LCD_RESET
686 string "LCD panel reset pin"
690 Set the reset pin for the LCD panel. This takes a string in the format
691 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
693 config VIDEO_LCD_BL_EN
694 string "LCD panel backlight enable pin"
698 Set the backlight enable pin for the LCD panel. This takes a string in the
699 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
702 config VIDEO_LCD_BL_PWM
703 string "LCD panel backlight pwm pin"
707 Set the backlight pwm pin for the LCD panel. This takes a string in the
708 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
710 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
711 bool "LCD panel backlight pwm is inverted"
715 Set this if the backlight pwm output is active low.
717 config VIDEO_LCD_PANEL_I2C
718 bool "LCD panel needs to be configured via i2c"
723 Say y here if the LCD panel needs to be configured via i2c. This
724 will add a bitbang i2c controller using gpios to talk to the LCD.
726 config VIDEO_LCD_PANEL_I2C_SDA
727 string "LCD panel i2c interface SDA pin"
728 depends on VIDEO_LCD_PANEL_I2C
731 Set the SDA pin for the LCD i2c interface. This takes a string in the
732 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
734 config VIDEO_LCD_PANEL_I2C_SCL
735 string "LCD panel i2c interface SCL pin"
736 depends on VIDEO_LCD_PANEL_I2C
739 Set the SCL pin for the LCD i2c interface. This takes a string in the
740 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
743 # Note only one of these may be selected at a time! But hidden choices are
744 # not supported by Kconfig
745 config VIDEO_LCD_IF_PARALLEL
748 config VIDEO_LCD_IF_LVDS
756 bool "Display Engine 2 video driver"
762 Say y here if you want to build DE2 video driver which is present on
763 newer SoCs. Currently only HDMI output is supported.
767 prompt "LCD panel support"
770 Select which type of LCD panel to support.
772 config VIDEO_LCD_PANEL_PARALLEL
773 bool "Generic parallel interface LCD panel"
774 select VIDEO_LCD_IF_PARALLEL
776 config VIDEO_LCD_PANEL_LVDS
777 bool "Generic lvds interface LCD panel"
778 select VIDEO_LCD_IF_LVDS
780 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
781 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
782 select VIDEO_LCD_SSD2828
783 select VIDEO_LCD_IF_PARALLEL
785 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
787 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
788 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
789 select VIDEO_LCD_ANX9804
790 select VIDEO_LCD_IF_PARALLEL
791 select VIDEO_LCD_PANEL_I2C
793 Select this for eDP LCD panels with 4 lanes running at 1.62G,
794 connected via an ANX9804 bridge chip.
796 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
797 bool "Hitachi tx18d42vm LCD panel"
798 select VIDEO_LCD_HITACHI_TX18D42VM
799 select VIDEO_LCD_IF_LVDS
801 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
803 config VIDEO_LCD_TL059WV5C0
804 bool "tl059wv5c0 LCD panel"
805 select VIDEO_LCD_PANEL_I2C
806 select VIDEO_LCD_IF_PARALLEL
808 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
809 Aigo M60/M608/M606 tablets.
814 string "SATA power pin"
817 Set the pins used to power the SATA. This takes a string in the
818 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
822 int "GMAC Transmit Clock Delay Chain"
825 Set the GMAC Transmit Clock Delay Chain value.
827 config SPL_STACK_R_ADDR
828 default 0x4fe00000 if MACH_SUN4I
829 default 0x4fe00000 if MACH_SUN5I
830 default 0x4fe00000 if MACH_SUN6I
831 default 0x4fe00000 if MACH_SUN7I
832 default 0x4fe00000 if MACH_SUN8I
833 default 0x2fe00000 if MACH_SUN9I
834 default 0x4fe00000 if MACH_SUN50I