4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
10 bool "Allwinner sun6i internal P2WI controller"
12 If you say yes to this option, support will be included for the
13 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
15 The P2WI looks like an SMBus controller (which supports only byte
16 accesses), except that it only supports one slave device.
17 This interface is used to connect to specific PMIC devices (like the
23 Support for the PRCM (Power/Reset/Clock Management) unit available
27 bool "Allwinner sunXi Reduced Serial Bus Driver"
29 Say y here to enable support for Allwinner's Reduced Serial Bus
30 (RSB) support. This controller is responsible for communicating
31 with various RSB based devices, such as AXP223, AXP8XX PMICs,
34 config SUNXI_HIGH_SRAM
38 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
39 with the first SRAM region being located at address 0.
40 Some newer SoCs map the boot ROM at address 0 instead and move the
41 SRAM to 64KB, just behind the mask ROM.
42 Chips using the latter setup are supposed to select this option to
43 adjust the addresses accordingly.
45 # Note only one of these may be selected at a time! But hidden choices are
46 # not supported by Kconfig
47 config SUNXI_GEN_SUN4I
50 Select this for sunxi SoCs which have resets and clocks set up
51 as the original A10 (mach-sun4i).
53 config SUNXI_GEN_SUN6I
56 Select this for sunxi SoCs which have sun6i like periphery, like
57 separate ahb reset control registers, custom pmic bus, new style
63 Select this for sunxi SoCs which uses a DRAM controller like the
64 DesignWare controller used in H3, mainly SoCs after H3, which do
65 not have official open-source DRAM initialization code, but can
66 use modified H3 DRAM initialization code.
69 config SUNXI_DRAM_DW_16BIT
72 Select this for sunxi SoCs with DesignWare DRAM controller and
73 have only 16-bit memory buswidth.
75 config SUNXI_DRAM_DW_32BIT
78 Select this for sunxi SoCs with DesignWare DRAM controller with
79 32-bit memory buswidth.
82 config MACH_SUNXI_H3_H5
87 select SUNXI_DRAM_DW_32BIT
88 select SUNXI_GEN_SUN6I
92 prompt "Sunxi SoC Variant"
96 bool "sun4i (Allwinner A10)"
98 select ARM_CORTEX_CPU_IS_UP
99 select SUNXI_GEN_SUN4I
103 bool "sun5i (Allwinner A13)"
105 select ARM_CORTEX_CPU_IS_UP
106 select SUNXI_GEN_SUN4I
108 imply CONS_INDEX_2 if !DM_SERIAL
111 bool "sun6i (Allwinner A31)"
113 select CPU_V7_HAS_NONSEC
114 select CPU_V7_HAS_VIRT
115 select ARCH_SUPPORT_PSCI
118 select SUNXI_GEN_SUN6I
120 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
123 bool "sun7i (Allwinner A20)"
125 select CPU_V7_HAS_NONSEC
126 select CPU_V7_HAS_VIRT
127 select ARCH_SUPPORT_PSCI
128 select SUNXI_GEN_SUN4I
130 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
132 config MACH_SUN8I_A23
133 bool "sun8i (Allwinner A23)"
135 select CPU_V7_HAS_NONSEC
136 select CPU_V7_HAS_VIRT
137 select ARCH_SUPPORT_PSCI
138 select SUNXI_GEN_SUN6I
140 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
141 imply CONS_INDEX_5 if !DM_SERIAL
143 config MACH_SUN8I_A33
144 bool "sun8i (Allwinner A33)"
146 select CPU_V7_HAS_NONSEC
147 select CPU_V7_HAS_VIRT
148 select ARCH_SUPPORT_PSCI
149 select SUNXI_GEN_SUN6I
151 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
152 imply CONS_INDEX_5 if !DM_SERIAL
154 config MACH_SUN8I_A83T
155 bool "sun8i (Allwinner A83T)"
157 select SUNXI_GEN_SUN6I
158 select MMC_SUNXI_HAS_NEW_MODE
162 bool "sun8i (Allwinner H3)"
164 select CPU_V7_HAS_NONSEC
165 select CPU_V7_HAS_VIRT
166 select ARCH_SUPPORT_PSCI
167 select MACH_SUNXI_H3_H5
168 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
170 config MACH_SUN8I_R40
171 bool "sun8i (Allwinner R40)"
173 select CPU_V7_HAS_NONSEC
174 select CPU_V7_HAS_VIRT
175 select ARCH_SUPPORT_PSCI
176 select SUNXI_GEN_SUN6I
179 select SUNXI_DRAM_DW_32BIT
181 config MACH_SUN8I_V3S
182 bool "sun8i (Allwinner V3s)"
184 select CPU_V7_HAS_NONSEC
185 select CPU_V7_HAS_VIRT
186 select ARCH_SUPPORT_PSCI
187 select SUNXI_GEN_SUN6I
189 select SUNXI_DRAM_DW_16BIT
191 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
194 bool "sun9i (Allwinner A80)"
197 select SUNXI_HIGH_SRAM
198 select SUNXI_GEN_SUN6I
203 bool "sun50i (Allwinner A64)"
207 select SUNXI_GEN_SUN6I
208 select SUNXI_HIGH_SRAM
211 select SUNXI_DRAM_DW_32BIT
215 config MACH_SUN50I_H5
216 bool "sun50i (Allwinner H5)"
218 select MACH_SUNXI_H3_H5
219 select SUNXI_HIGH_SRAM
225 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
230 default y if MACH_SUN8I_A23
231 default y if MACH_SUN8I_A33
232 default y if MACH_SUN8I_A83T
233 default y if MACH_SUNXI_H3_H5
234 default y if MACH_SUN8I_R40
235 default y if MACH_SUN8I_V3S
237 config RESERVE_ALLWINNER_BOOT0_HEADER
238 bool "reserve space for Allwinner boot0 header"
239 select ENABLE_ARM_SOC_BOOT0_HOOK
241 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
242 filled with magic values post build. The Allwinner provided boot0
243 blob relies on this information to load and execute U-Boot.
244 Only needed on 64-bit Allwinner boards so far when using boot0.
246 config ARM_BOOT_HOOK_RMR
250 select ENABLE_ARM_SOC_BOOT0_HOOK
252 Insert some ARM32 code at the very beginning of the U-Boot binary
253 which uses an RMR register write to bring the core into AArch64 mode.
254 The very first instruction acts as a switch, since it's carefully
255 chosen to be a NOP in one mode and a branch in the other, so the
256 code would only be executed if not already in AArch64.
257 This allows both the SPL and the U-Boot proper to be entered in
258 either mode and switch to AArch64 if needed.
261 config SUNXI_DRAM_DDR3
264 config SUNXI_DRAM_DDR2
267 config SUNXI_DRAM_LPDDR3
271 prompt "DRAM Type and Timing"
272 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
273 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
275 config SUNXI_DRAM_DDR3_1333
277 select SUNXI_DRAM_DDR3
278 depends on !MACH_SUN8I_V3S
280 This option is the original only supported memory type, which suits
281 many H3/H5/A64 boards available now.
283 config SUNXI_DRAM_LPDDR3_STOCK
284 bool "LPDDR3 with Allwinner stock configuration"
285 select SUNXI_DRAM_LPDDR3
287 This option is the LPDDR3 timing used by the stock boot0 by
290 config SUNXI_DRAM_DDR2_V3S
291 bool "DDR2 found in V3s chip"
292 select SUNXI_DRAM_DDR2
293 depends on MACH_SUN8I_V3S
295 This option is only for the DDR2 memory chip which is co-packaged in
302 int "sunxi dram type"
303 depends on MACH_SUN8I_A83T
306 Set the dram type, 3: DDR3, 7: LPDDR3
309 int "sunxi dram clock speed"
310 default 792 if MACH_SUN9I
311 default 648 if MACH_SUN8I_R40
312 default 312 if MACH_SUN6I || MACH_SUN8I
313 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
315 default 672 if MACH_SUN50I
317 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
318 must be a multiple of 24. For the sun9i (A80), the tested values
319 (for DDR3-1600) are 312 to 792.
321 if MACH_SUN5I || MACH_SUN7I
323 int "sunxi mbus clock speed"
326 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
331 int "sunxi dram zq value"
332 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
333 default 127 if MACH_SUN7I
334 default 14779 if MACH_SUN8I_V3S
335 default 3881979 if MACH_SUN8I_R40
336 default 4145117 if MACH_SUN9I
337 default 3881915 if MACH_SUN50I
339 Set the dram zq value.
342 bool "sunxi dram odt enable"
343 default n if !MACH_SUN8I_A23
344 default y if MACH_SUN8I_A23
345 default y if MACH_SUN8I_R40
346 default y if MACH_SUN50I
348 Select this to enable dram odt (on die termination).
350 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
352 int "sunxi dram emr1 value"
353 default 0 if MACH_SUN4I
354 default 4 if MACH_SUN5I || MACH_SUN7I
356 Set the dram controller emr1 value.
359 hex "sunxi dram tpr3 value"
362 Set the dram controller tpr3 parameter. This parameter configures
363 the delay on the command lane and also phase shifts, which are
364 applied for sampling incoming read data. The default value 0
365 means that no phase/delay adjustments are necessary. Properly
366 configuring this parameter increases reliability at high DRAM
369 config DRAM_DQS_GATING_DELAY
370 hex "sunxi dram dqs_gating_delay value"
373 Set the dram controller dqs_gating_delay parmeter. Each byte
374 encodes the DQS gating delay for each byte lane. The delay
375 granularity is 1/4 cycle. For example, the value 0x05060606
376 means that the delay is 5 quarter-cycles for one lane (1.25
377 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
378 The default value 0 means autodetection. The results of hardware
379 autodetection are not very reliable and depend on the chip
380 temperature (sometimes producing different results on cold start
381 and warm reboot). But the accuracy of hardware autodetection
382 is usually good enough, unless running at really high DRAM
383 clocks speeds (up to 600MHz). If unsure, keep as 0.
386 prompt "sunxi dram timings"
387 default DRAM_TIMINGS_VENDOR_MAGIC
389 Select the timings of the DDR3 chips.
391 config DRAM_TIMINGS_VENDOR_MAGIC
392 bool "Magic vendor timings from Android"
394 The same DRAM timings as in the Allwinner boot0 bootloader.
396 config DRAM_TIMINGS_DDR3_1066F_1333H
397 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
399 Use the timings of the standard JEDEC DDR3-1066F speed bin for
400 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
401 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
402 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
403 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
404 that down binning to DDR3-1066F is supported (because DDR3-1066F
405 uses a bit faster timings than DDR3-1333H).
407 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
408 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
410 Use the timings of the slowest possible JEDEC speed bin for the
411 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
412 DDR3-800E, DDR3-1066G or DDR3-1333J.
419 config DRAM_ODT_CORRECTION
420 int "sunxi dram odt correction value"
423 Set the dram odt correction value (range -255 - 255). In allwinner
424 fex files, this option is found in bits 8-15 of the u32 odt_en variable
425 in the [dram] section. When bit 31 of the odt_en variable is set
426 then the correction is negative. Usually the value for this is 0.
430 default 1008000000 if MACH_SUN4I
431 default 1008000000 if MACH_SUN5I
432 default 1008000000 if MACH_SUN6I
433 default 912000000 if MACH_SUN7I
434 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
435 default 1008000000 if MACH_SUN8I
436 default 1008000000 if MACH_SUN9I
438 config SYS_CONFIG_NAME
439 default "sun4i" if MACH_SUN4I
440 default "sun5i" if MACH_SUN5I
441 default "sun6i" if MACH_SUN6I
442 default "sun7i" if MACH_SUN7I
443 default "sun8i" if MACH_SUN8I
444 default "sun9i" if MACH_SUN9I
445 default "sun50i" if MACH_SUN50I
454 bool "UART0 on MicroSD breakout board"
457 Repurpose the SD card slot for getting access to the UART0 serial
458 console. Primarily useful only for low level u-boot debugging on
459 tablets, where normal UART0 is difficult to access and requires
460 device disassembly and/or soldering. As the SD card can't be used
461 at the same time, the system can be only booted in the FEL mode.
462 Only enable this if you really know what you are doing.
464 config OLD_SUNXI_KERNEL_COMPAT
465 bool "Enable workarounds for booting old kernels"
468 Set this to enable various workarounds for old kernels, this results in
469 sub-optimal settings for newer kernels, only enable if needed.
472 string "MAC power pin"
475 Set the pin used to power the MAC. This takes a string in the format
476 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
479 string "Card detect pin for mmc0"
480 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
483 Set the card detect pin for mmc0, leave empty to not use cd. This
484 takes a string in the format understood by sunxi_name_to_gpio, e.g.
485 PH1 for pin 1 of port H.
488 string "Card detect pin for mmc1"
491 See MMC0_CD_PIN help text.
494 string "Card detect pin for mmc2"
497 See MMC0_CD_PIN help text.
500 string "Card detect pin for mmc3"
503 See MMC0_CD_PIN help text.
506 string "Pins for mmc1"
509 Set the pins used for mmc1, when applicable. This takes a string in the
510 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
513 string "Pins for mmc2"
516 See MMC1_PINS help text.
519 string "Pins for mmc3"
522 See MMC1_PINS help text.
524 config MMC_SUNXI_SLOT_EXTRA
525 int "mmc extra slot number"
528 sunxi builds always enable mmc0, some boards also have a second sdcard
529 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
532 config INITIAL_USB_SCAN_DELAY
533 int "delay initial usb scan by x ms to allow builtin devices to init"
536 Some boards have on board usb devices which need longer than the
537 USB spec's 1 second to connect from board powerup. Set this config
538 option to a non 0 value to add an extra delay before the first usb
542 string "Vbus enable pin for usb0 (otg)"
545 Set the Vbus enable pin for usb0 (otg). This takes a string in the
546 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
549 string "Vbus detect pin for usb0 (otg)"
552 Set the Vbus detect pin for usb0 (otg). This takes a string in the
553 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
556 string "ID detect pin for usb0 (otg)"
559 Set the ID detect pin for usb0 (otg). This takes a string in the
560 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
563 string "Vbus enable pin for usb1 (ehci0)"
564 default "PH6" if MACH_SUN4I || MACH_SUN7I
565 default "PH27" if MACH_SUN6I
567 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
568 a string in the format understood by sunxi_name_to_gpio, e.g.
569 PH1 for pin 1 of port H.
572 string "Vbus enable pin for usb2 (ehci1)"
573 default "PH3" if MACH_SUN4I || MACH_SUN7I
574 default "PH24" if MACH_SUN6I
576 See USB1_VBUS_PIN help text.
579 string "Vbus enable pin for usb3 (ehci2)"
582 See USB1_VBUS_PIN help text.
585 bool "Enable I2C/TWI controller 0"
586 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
587 default n if MACH_SUN6I || MACH_SUN8I
590 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
591 its clock and setting up the bus. This is especially useful on devices
592 with slaves connected to the bus or with pins exposed through e.g. an
593 expansion port/header.
596 bool "Enable I2C/TWI controller 1"
600 See I2C0_ENABLE help text.
603 bool "Enable I2C/TWI controller 2"
607 See I2C0_ENABLE help text.
609 if MACH_SUN6I || MACH_SUN7I
611 bool "Enable I2C/TWI controller 3"
615 See I2C0_ENABLE help text.
620 bool "Enable the PRCM I2C/TWI controller"
621 # This is used for the pmic on H3
622 default y if SY8106A_POWER
625 Set this to y to enable the I2C controller which is part of the PRCM.
630 bool "Enable I2C/TWI controller 4"
634 See I2C0_ENABLE help text.
638 bool "Enable support for gpio-s on axp PMICs"
641 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
644 bool "Enable graphical uboot console on HDMI, LCD or VGA"
645 depends on !MACH_SUN8I_A83T
646 depends on !MACH_SUNXI_H3_H5
647 depends on !MACH_SUN8I_R40
648 depends on !MACH_SUN8I_V3S
649 depends on !MACH_SUN9I
650 depends on !MACH_SUN50I
652 imply VIDEO_DT_SIMPLEFB
655 Say Y here to add support for using a cfb console on the HDMI, LCD
656 or VGA output found on most sunxi devices. See doc/README.video for
657 info on how to select the video output and mode.
660 bool "HDMI output support"
661 depends on VIDEO_SUNXI && !MACH_SUN8I
664 Say Y here to add support for outputting video over HDMI.
667 bool "VGA output support"
668 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
671 Say Y here to add support for outputting video over VGA.
673 config VIDEO_VGA_VIA_LCD
674 bool "VGA via LCD controller support"
675 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
678 Say Y here to add support for external DACs connected to the parallel
679 LCD interface driving a VGA connector, such as found on the
682 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
683 bool "Force sync active high for VGA via LCD controller support"
684 depends on VIDEO_VGA_VIA_LCD
687 Say Y here if you've a board which uses opendrain drivers for the vga
688 hsync and vsync signals. Opendrain drivers cannot generate steep enough
689 positive edges for a stable video output, so on boards with opendrain
690 drivers the sync signals must always be active high.
692 config VIDEO_VGA_EXTERNAL_DAC_EN
693 string "LCD panel power enable pin"
694 depends on VIDEO_VGA_VIA_LCD
697 Set the enable pin for the external VGA DAC. This takes a string in the
698 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
700 config VIDEO_COMPOSITE
701 bool "Composite video output support"
702 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
705 Say Y here to add support for outputting composite video.
707 config VIDEO_LCD_MODE
708 string "LCD panel timing details"
709 depends on VIDEO_SUNXI
712 LCD panel timing details string, leave empty if there is no LCD panel.
713 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
714 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
715 Also see: http://linux-sunxi.org/LCD
717 config VIDEO_LCD_DCLK_PHASE
718 int "LCD panel display clock phase"
719 depends on VIDEO_SUNXI || DM_VIDEO
722 Select LCD panel display clock phase shift, range 0-3.
724 config VIDEO_LCD_POWER
725 string "LCD panel power enable pin"
726 depends on VIDEO_SUNXI
729 Set the power enable pin for the LCD panel. This takes a string in the
730 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
732 config VIDEO_LCD_RESET
733 string "LCD panel reset pin"
734 depends on VIDEO_SUNXI
737 Set the reset pin for the LCD panel. This takes a string in the format
738 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
740 config VIDEO_LCD_BL_EN
741 string "LCD panel backlight enable pin"
742 depends on VIDEO_SUNXI
745 Set the backlight enable pin for the LCD panel. This takes a string in the
746 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
749 config VIDEO_LCD_BL_PWM
750 string "LCD panel backlight pwm pin"
751 depends on VIDEO_SUNXI
754 Set the backlight pwm pin for the LCD panel. This takes a string in the
755 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
757 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
758 bool "LCD panel backlight pwm is inverted"
759 depends on VIDEO_SUNXI
762 Set this if the backlight pwm output is active low.
764 config VIDEO_LCD_PANEL_I2C
765 bool "LCD panel needs to be configured via i2c"
766 depends on VIDEO_SUNXI
770 Say y here if the LCD panel needs to be configured via i2c. This
771 will add a bitbang i2c controller using gpios to talk to the LCD.
773 config VIDEO_LCD_PANEL_I2C_SDA
774 string "LCD panel i2c interface SDA pin"
775 depends on VIDEO_LCD_PANEL_I2C
778 Set the SDA pin for the LCD i2c interface. This takes a string in the
779 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
781 config VIDEO_LCD_PANEL_I2C_SCL
782 string "LCD panel i2c interface SCL pin"
783 depends on VIDEO_LCD_PANEL_I2C
786 Set the SCL pin for the LCD i2c interface. This takes a string in the
787 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
790 # Note only one of these may be selected at a time! But hidden choices are
791 # not supported by Kconfig
792 config VIDEO_LCD_IF_PARALLEL
795 config VIDEO_LCD_IF_LVDS
803 bool "Display Engine 2 video driver"
807 imply VIDEO_DT_SIMPLEFB
810 Say y here if you want to build DE2 video driver which is present on
811 newer SoCs. Currently only HDMI output is supported.
815 prompt "LCD panel support"
816 depends on VIDEO_SUNXI
818 Select which type of LCD panel to support.
820 config VIDEO_LCD_PANEL_PARALLEL
821 bool "Generic parallel interface LCD panel"
822 select VIDEO_LCD_IF_PARALLEL
824 config VIDEO_LCD_PANEL_LVDS
825 bool "Generic lvds interface LCD panel"
826 select VIDEO_LCD_IF_LVDS
828 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
829 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
830 select VIDEO_LCD_SSD2828
831 select VIDEO_LCD_IF_PARALLEL
833 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
835 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
836 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
837 select VIDEO_LCD_ANX9804
838 select VIDEO_LCD_IF_PARALLEL
839 select VIDEO_LCD_PANEL_I2C
841 Select this for eDP LCD panels with 4 lanes running at 1.62G,
842 connected via an ANX9804 bridge chip.
844 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
845 bool "Hitachi tx18d42vm LCD panel"
846 select VIDEO_LCD_HITACHI_TX18D42VM
847 select VIDEO_LCD_IF_LVDS
849 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
851 config VIDEO_LCD_TL059WV5C0
852 bool "tl059wv5c0 LCD panel"
853 select VIDEO_LCD_PANEL_I2C
854 select VIDEO_LCD_IF_PARALLEL
856 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
857 Aigo M60/M608/M606 tablets.
862 string "SATA power pin"
865 Set the pins used to power the SATA. This takes a string in the
866 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
870 int "GMAC Transmit Clock Delay Chain"
873 Set the GMAC Transmit Clock Delay Chain value.
875 config SPL_STACK_R_ADDR
876 default 0x4fe00000 if MACH_SUN4I
877 default 0x4fe00000 if MACH_SUN5I
878 default 0x4fe00000 if MACH_SUN6I
879 default 0x4fe00000 if MACH_SUN7I
880 default 0x4fe00000 if MACH_SUN8I
881 default 0x2fe00000 if MACH_SUN9I
882 default 0x4fe00000 if MACH_SUN50I
885 bool "Support for SPI Flash on Allwinner SoCs in SPL"
886 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
888 Enable support for SPI Flash. This option allows SPL to read from
889 sunxi SPI Flash. It uses the same method as the boot ROM, so does
890 not need any extra configuration.