4 default " Allwinner Technology"
10 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
11 with the first SRAM region being located at address 0.
12 Some newer SoCs map the boot ROM at address 0 instead and move the
13 SRAM to 64KB, just behind the mask ROM.
14 Chips using the latter setup are supposed to select this option to
15 adjust the addresses accordingly.
17 # Note only one of these may be selected at a time! But hidden choices are
18 # not supported by Kconfig
19 config SUNXI_GEN_SUN4I
22 Select this for sunxi SoCs which have resets and clocks set up
23 as the original A10 (mach-sun4i).
25 config SUNXI_GEN_SUN6I
28 Select this for sunxi SoCs which have sun6i like periphery, like
29 separate ahb reset control registers, custom pmic bus, new style
35 Select this for sunxi SoCs which uses a DRAM controller like the
36 DesignWare controller used in H3, mainly SoCs after H3, which do
37 not have official open-source DRAM initialization code, but can
38 use modified H3 DRAM initialization code.
41 config SUNXI_DRAM_DW_16BIT
44 Select this for sunxi SoCs with DesignWare DRAM controller and
45 have only 16-bit memory buswidth.
47 config SUNXI_DRAM_DW_32BIT
50 Select this for sunxi SoCs with DesignWare DRAM controller with
51 32-bit memory buswidth.
54 config MACH_SUNXI_H3_H5
59 select SUNXI_DRAM_DW_32BIT
60 select SUNXI_GEN_SUN6I
64 prompt "Sunxi SoC Variant"
68 bool "sun4i (Allwinner A10)"
70 select ARM_CORTEX_CPU_IS_UP
71 select SUNXI_GEN_SUN4I
75 bool "sun5i (Allwinner A13)"
77 select ARM_CORTEX_CPU_IS_UP
78 select SUNXI_GEN_SUN4I
82 bool "sun6i (Allwinner A31)"
84 select CPU_V7_HAS_NONSEC
85 select CPU_V7_HAS_VIRT
86 select ARCH_SUPPORT_PSCI
87 select SUNXI_GEN_SUN6I
89 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
92 bool "sun7i (Allwinner A20)"
94 select CPU_V7_HAS_NONSEC
95 select CPU_V7_HAS_VIRT
96 select ARCH_SUPPORT_PSCI
97 select SUNXI_GEN_SUN4I
99 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
101 config MACH_SUN8I_A23
102 bool "sun8i (Allwinner A23)"
104 select CPU_V7_HAS_NONSEC
105 select CPU_V7_HAS_VIRT
106 select ARCH_SUPPORT_PSCI
107 select SUNXI_GEN_SUN6I
109 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
111 config MACH_SUN8I_A33
112 bool "sun8i (Allwinner A33)"
114 select CPU_V7_HAS_NONSEC
115 select CPU_V7_HAS_VIRT
116 select ARCH_SUPPORT_PSCI
117 select SUNXI_GEN_SUN6I
119 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
121 config MACH_SUN8I_A83T
122 bool "sun8i (Allwinner A83T)"
124 select SUNXI_GEN_SUN6I
128 bool "sun8i (Allwinner H3)"
130 select CPU_V7_HAS_NONSEC
131 select CPU_V7_HAS_VIRT
132 select ARCH_SUPPORT_PSCI
133 select MACH_SUNXI_H3_H5
134 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
136 config MACH_SUN8I_R40
137 bool "sun8i (Allwinner R40)"
139 select CPU_V7_HAS_NONSEC
140 select CPU_V7_HAS_VIRT
141 select ARCH_SUPPORT_PSCI
142 select SUNXI_GEN_SUN6I
145 select SUNXI_DRAM_DW_32BIT
147 config MACH_SUN8I_V3S
148 bool "sun8i (Allwinner V3s)"
150 select CPU_V7_HAS_NONSEC
151 select CPU_V7_HAS_VIRT
152 select ARCH_SUPPORT_PSCI
153 select SUNXI_GEN_SUN6I
154 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
157 bool "sun9i (Allwinner A80)"
159 select SUNXI_HIGH_SRAM
160 select SUNXI_GEN_SUN6I
164 bool "sun50i (Allwinner A64)"
168 select SUNXI_GEN_SUN6I
169 select SUNXI_HIGH_SRAM
172 select SUNXI_DRAM_DW_32BIT
176 config MACH_SUN50I_H5
177 bool "sun50i (Allwinner H5)"
179 select MACH_SUNXI_H3_H5
180 select SUNXI_HIGH_SRAM
186 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
189 default y if MACH_SUN8I_A23
190 default y if MACH_SUN8I_A33
191 default y if MACH_SUN8I_A83T
192 default y if MACH_SUNXI_H3_H5
193 default y if MACH_SUN8I_R40
194 default y if MACH_SUN8I_V3S
196 config RESERVE_ALLWINNER_BOOT0_HEADER
197 bool "reserve space for Allwinner boot0 header"
198 select ENABLE_ARM_SOC_BOOT0_HOOK
200 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
201 filled with magic values post build. The Allwinner provided boot0
202 blob relies on this information to load and execute U-Boot.
203 Only needed on 64-bit Allwinner boards so far when using boot0.
205 config ARM_BOOT_HOOK_RMR
209 select ENABLE_ARM_SOC_BOOT0_HOOK
211 Insert some ARM32 code at the very beginning of the U-Boot binary
212 which uses an RMR register write to bring the core into AArch64 mode.
213 The very first instruction acts as a switch, since it's carefully
214 chosen to be a NOP in one mode and a branch in the other, so the
215 code would only be executed if not already in AArch64.
216 This allows both the SPL and the U-Boot proper to be entered in
217 either mode and switch to AArch64 if needed.
220 config SUNXI_DRAM_DDR3
223 config SUNXI_DRAM_DDR2
227 prompt "DRAM Type and Timing"
228 default SUNXI_DRAM_DDR3_1333
230 config SUNXI_DRAM_DDR3_1333
232 select SUNXI_DRAM_DDR3
234 This option is the original only supported memory type, which suits
235 many H3/H5/A64 boards available now.
237 config SUNXI_DRAM_DDR2_V3S
238 bool "DDR2 found in V3s chip"
239 select SUNXI_DRAM_DDR2
241 This option is only for the DDR2 memory chip which is co-packaged in
248 int "sunxi dram type"
249 depends on MACH_SUN8I_A83T
252 Set the dram type, 3: DDR3, 7: LPDDR3
255 int "sunxi dram clock speed"
256 default 792 if MACH_SUN9I
257 default 648 if MACH_SUN8I_R40
258 default 312 if MACH_SUN6I || MACH_SUN8I
259 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
260 default 672 if MACH_SUN50I
262 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
263 must be a multiple of 24. For the sun9i (A80), the tested values
264 (for DDR3-1600) are 312 to 792.
266 if MACH_SUN5I || MACH_SUN7I
268 int "sunxi mbus clock speed"
271 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
276 int "sunxi dram zq value"
277 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
278 default 127 if MACH_SUN7I
279 default 3881979 if MACH_SUN8I_R40
280 default 4145117 if MACH_SUN9I
281 default 3881915 if MACH_SUN50I
283 Set the dram zq value.
286 bool "sunxi dram odt enable"
287 default n if !MACH_SUN8I_A23
288 default y if MACH_SUN8I_A23
289 default y if MACH_SUN8I_R40
290 default y if MACH_SUN50I
292 Select this to enable dram odt (on die termination).
294 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
296 int "sunxi dram emr1 value"
297 default 0 if MACH_SUN4I
298 default 4 if MACH_SUN5I || MACH_SUN7I
300 Set the dram controller emr1 value.
303 hex "sunxi dram tpr3 value"
306 Set the dram controller tpr3 parameter. This parameter configures
307 the delay on the command lane and also phase shifts, which are
308 applied for sampling incoming read data. The default value 0
309 means that no phase/delay adjustments are necessary. Properly
310 configuring this parameter increases reliability at high DRAM
313 config DRAM_DQS_GATING_DELAY
314 hex "sunxi dram dqs_gating_delay value"
317 Set the dram controller dqs_gating_delay parmeter. Each byte
318 encodes the DQS gating delay for each byte lane. The delay
319 granularity is 1/4 cycle. For example, the value 0x05060606
320 means that the delay is 5 quarter-cycles for one lane (1.25
321 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
322 The default value 0 means autodetection. The results of hardware
323 autodetection are not very reliable and depend on the chip
324 temperature (sometimes producing different results on cold start
325 and warm reboot). But the accuracy of hardware autodetection
326 is usually good enough, unless running at really high DRAM
327 clocks speeds (up to 600MHz). If unsure, keep as 0.
330 prompt "sunxi dram timings"
331 default DRAM_TIMINGS_VENDOR_MAGIC
333 Select the timings of the DDR3 chips.
335 config DRAM_TIMINGS_VENDOR_MAGIC
336 bool "Magic vendor timings from Android"
338 The same DRAM timings as in the Allwinner boot0 bootloader.
340 config DRAM_TIMINGS_DDR3_1066F_1333H
341 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
343 Use the timings of the standard JEDEC DDR3-1066F speed bin for
344 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
345 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
346 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
347 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
348 that down binning to DDR3-1066F is supported (because DDR3-1066F
349 uses a bit faster timings than DDR3-1333H).
351 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
352 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
354 Use the timings of the slowest possible JEDEC speed bin for the
355 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
356 DDR3-800E, DDR3-1066G or DDR3-1333J.
363 config DRAM_ODT_CORRECTION
364 int "sunxi dram odt correction value"
367 Set the dram odt correction value (range -255 - 255). In allwinner
368 fex files, this option is found in bits 8-15 of the u32 odt_en variable
369 in the [dram] section. When bit 31 of the odt_en variable is set
370 then the correction is negative. Usually the value for this is 0.
374 default 1008000000 if MACH_SUN4I
375 default 1008000000 if MACH_SUN5I
376 default 1008000000 if MACH_SUN6I
377 default 912000000 if MACH_SUN7I
378 default 1008000000 if MACH_SUN8I
379 default 1008000000 if MACH_SUN9I
380 default 816000000 if MACH_SUN50I
382 config SYS_CONFIG_NAME
383 default "sun4i" if MACH_SUN4I
384 default "sun5i" if MACH_SUN5I
385 default "sun6i" if MACH_SUN6I
386 default "sun7i" if MACH_SUN7I
387 default "sun8i" if MACH_SUN8I
388 default "sun9i" if MACH_SUN9I
389 default "sun50i" if MACH_SUN50I
398 bool "UART0 on MicroSD breakout board"
401 Repurpose the SD card slot for getting access to the UART0 serial
402 console. Primarily useful only for low level u-boot debugging on
403 tablets, where normal UART0 is difficult to access and requires
404 device disassembly and/or soldering. As the SD card can't be used
405 at the same time, the system can be only booted in the FEL mode.
406 Only enable this if you really know what you are doing.
408 config OLD_SUNXI_KERNEL_COMPAT
409 bool "Enable workarounds for booting old kernels"
412 Set this to enable various workarounds for old kernels, this results in
413 sub-optimal settings for newer kernels, only enable if needed.
416 string "MAC power pin"
419 Set the pin used to power the MAC. This takes a string in the format
420 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
423 string "Card detect pin for mmc0"
424 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
427 Set the card detect pin for mmc0, leave empty to not use cd. This
428 takes a string in the format understood by sunxi_name_to_gpio, e.g.
429 PH1 for pin 1 of port H.
432 string "Card detect pin for mmc1"
435 See MMC0_CD_PIN help text.
438 string "Card detect pin for mmc2"
441 See MMC0_CD_PIN help text.
444 string "Card detect pin for mmc3"
447 See MMC0_CD_PIN help text.
450 string "Pins for mmc1"
453 Set the pins used for mmc1, when applicable. This takes a string in the
454 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
457 string "Pins for mmc2"
460 See MMC1_PINS help text.
463 string "Pins for mmc3"
466 See MMC1_PINS help text.
468 config MMC_SUNXI_SLOT_EXTRA
469 int "mmc extra slot number"
472 sunxi builds always enable mmc0, some boards also have a second sdcard
473 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
476 config INITIAL_USB_SCAN_DELAY
477 int "delay initial usb scan by x ms to allow builtin devices to init"
480 Some boards have on board usb devices which need longer than the
481 USB spec's 1 second to connect from board powerup. Set this config
482 option to a non 0 value to add an extra delay before the first usb
486 string "Vbus enable pin for usb0 (otg)"
489 Set the Vbus enable pin for usb0 (otg). This takes a string in the
490 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
493 string "Vbus detect pin for usb0 (otg)"
496 Set the Vbus detect pin for usb0 (otg). This takes a string in the
497 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
500 string "ID detect pin for usb0 (otg)"
503 Set the ID detect pin for usb0 (otg). This takes a string in the
504 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
507 string "Vbus enable pin for usb1 (ehci0)"
508 default "PH6" if MACH_SUN4I || MACH_SUN7I
509 default "PH27" if MACH_SUN6I
511 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
512 a string in the format understood by sunxi_name_to_gpio, e.g.
513 PH1 for pin 1 of port H.
516 string "Vbus enable pin for usb2 (ehci1)"
517 default "PH3" if MACH_SUN4I || MACH_SUN7I
518 default "PH24" if MACH_SUN6I
520 See USB1_VBUS_PIN help text.
523 string "Vbus enable pin for usb3 (ehci2)"
526 See USB1_VBUS_PIN help text.
529 bool "Enable I2C/TWI controller 0"
530 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
531 default n if MACH_SUN6I || MACH_SUN8I
534 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
535 its clock and setting up the bus. This is especially useful on devices
536 with slaves connected to the bus or with pins exposed through e.g. an
537 expansion port/header.
540 bool "Enable I2C/TWI controller 1"
544 See I2C0_ENABLE help text.
547 bool "Enable I2C/TWI controller 2"
551 See I2C0_ENABLE help text.
553 if MACH_SUN6I || MACH_SUN7I
555 bool "Enable I2C/TWI controller 3"
559 See I2C0_ENABLE help text.
564 bool "Enable the PRCM I2C/TWI controller"
565 # This is used for the pmic on H3
566 default y if SY8106A_POWER
569 Set this to y to enable the I2C controller which is part of the PRCM.
574 bool "Enable I2C/TWI controller 4"
578 See I2C0_ENABLE help text.
582 bool "Enable support for gpio-s on axp PMICs"
585 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
588 bool "Enable graphical uboot console on HDMI, LCD or VGA"
589 depends on !MACH_SUN8I_A83T
590 depends on !MACH_SUNXI_H3_H5
591 depends on !MACH_SUN8I_R40
592 depends on !MACH_SUN8I_V3S
593 depends on !MACH_SUN9I
594 depends on !MACH_SUN50I
597 Say Y here to add support for using a cfb console on the HDMI, LCD
598 or VGA output found on most sunxi devices. See doc/README.video for
599 info on how to select the video output and mode.
602 bool "HDMI output support"
603 depends on VIDEO && !MACH_SUN8I
606 Say Y here to add support for outputting video over HDMI.
609 bool "VGA output support"
610 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
613 Say Y here to add support for outputting video over VGA.
615 config VIDEO_VGA_VIA_LCD
616 bool "VGA via LCD controller support"
617 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
620 Say Y here to add support for external DACs connected to the parallel
621 LCD interface driving a VGA connector, such as found on the
624 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
625 bool "Force sync active high for VGA via LCD controller support"
626 depends on VIDEO_VGA_VIA_LCD
629 Say Y here if you've a board which uses opendrain drivers for the vga
630 hsync and vsync signals. Opendrain drivers cannot generate steep enough
631 positive edges for a stable video output, so on boards with opendrain
632 drivers the sync signals must always be active high.
634 config VIDEO_VGA_EXTERNAL_DAC_EN
635 string "LCD panel power enable pin"
636 depends on VIDEO_VGA_VIA_LCD
639 Set the enable pin for the external VGA DAC. This takes a string in the
640 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
642 config VIDEO_COMPOSITE
643 bool "Composite video output support"
644 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
647 Say Y here to add support for outputting composite video.
649 config VIDEO_LCD_MODE
650 string "LCD panel timing details"
654 LCD panel timing details string, leave empty if there is no LCD panel.
655 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
656 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
657 Also see: http://linux-sunxi.org/LCD
659 config VIDEO_LCD_DCLK_PHASE
660 int "LCD panel display clock phase"
664 Select LCD panel display clock phase shift, range 0-3.
666 config VIDEO_LCD_POWER
667 string "LCD panel power enable pin"
671 Set the power enable pin for the LCD panel. This takes a string in the
672 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
674 config VIDEO_LCD_RESET
675 string "LCD panel reset pin"
679 Set the reset pin for the LCD panel. This takes a string in the format
680 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
682 config VIDEO_LCD_BL_EN
683 string "LCD panel backlight enable pin"
687 Set the backlight enable pin for the LCD panel. This takes a string in the
688 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
691 config VIDEO_LCD_BL_PWM
692 string "LCD panel backlight pwm pin"
696 Set the backlight pwm pin for the LCD panel. This takes a string in the
697 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
699 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
700 bool "LCD panel backlight pwm is inverted"
704 Set this if the backlight pwm output is active low.
706 config VIDEO_LCD_PANEL_I2C
707 bool "LCD panel needs to be configured via i2c"
712 Say y here if the LCD panel needs to be configured via i2c. This
713 will add a bitbang i2c controller using gpios to talk to the LCD.
715 config VIDEO_LCD_PANEL_I2C_SDA
716 string "LCD panel i2c interface SDA pin"
717 depends on VIDEO_LCD_PANEL_I2C
720 Set the SDA pin for the LCD i2c interface. This takes a string in the
721 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
723 config VIDEO_LCD_PANEL_I2C_SCL
724 string "LCD panel i2c interface SCL pin"
725 depends on VIDEO_LCD_PANEL_I2C
728 Set the SCL pin for the LCD i2c interface. This takes a string in the
729 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
732 # Note only one of these may be selected at a time! But hidden choices are
733 # not supported by Kconfig
734 config VIDEO_LCD_IF_PARALLEL
737 config VIDEO_LCD_IF_LVDS
745 bool "Display Engine 2 video driver"
751 Say y here if you want to build DE2 video driver which is present on
752 newer SoCs. Currently only HDMI output is supported.
756 prompt "LCD panel support"
759 Select which type of LCD panel to support.
761 config VIDEO_LCD_PANEL_PARALLEL
762 bool "Generic parallel interface LCD panel"
763 select VIDEO_LCD_IF_PARALLEL
765 config VIDEO_LCD_PANEL_LVDS
766 bool "Generic lvds interface LCD panel"
767 select VIDEO_LCD_IF_LVDS
769 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
770 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
771 select VIDEO_LCD_SSD2828
772 select VIDEO_LCD_IF_PARALLEL
774 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
776 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
777 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
778 select VIDEO_LCD_ANX9804
779 select VIDEO_LCD_IF_PARALLEL
780 select VIDEO_LCD_PANEL_I2C
782 Select this for eDP LCD panels with 4 lanes running at 1.62G,
783 connected via an ANX9804 bridge chip.
785 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
786 bool "Hitachi tx18d42vm LCD panel"
787 select VIDEO_LCD_HITACHI_TX18D42VM
788 select VIDEO_LCD_IF_LVDS
790 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
792 config VIDEO_LCD_TL059WV5C0
793 bool "tl059wv5c0 LCD panel"
794 select VIDEO_LCD_PANEL_I2C
795 select VIDEO_LCD_IF_PARALLEL
797 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
798 Aigo M60/M608/M606 tablets.
803 string "SATA power pin"
806 Set the pins used to power the SATA. This takes a string in the
807 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
811 int "GMAC Transmit Clock Delay Chain"
814 Set the GMAC Transmit Clock Delay Chain value.
816 config SPL_STACK_R_ADDR
817 default 0x4fe00000 if MACH_SUN4I
818 default 0x4fe00000 if MACH_SUN5I
819 default 0x4fe00000 if MACH_SUN6I
820 default 0x4fe00000 if MACH_SUN7I
821 default 0x4fe00000 if MACH_SUN8I
822 default 0x2fe00000 if MACH_SUN9I
823 default 0x4fe00000 if MACH_SUN50I