4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
13 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
14 with the first SRAM region being located at address 0.
15 Some newer SoCs map the boot ROM at address 0 instead and move the
16 SRAM to 64KB, just behind the mask ROM.
17 Chips using the latter setup are supposed to select this option to
18 adjust the addresses accordingly.
20 # Note only one of these may be selected at a time! But hidden choices are
21 # not supported by Kconfig
22 config SUNXI_GEN_SUN4I
25 Select this for sunxi SoCs which have resets and clocks set up
26 as the original A10 (mach-sun4i).
28 config SUNXI_GEN_SUN6I
31 Select this for sunxi SoCs which have sun6i like periphery, like
32 separate ahb reset control registers, custom pmic bus, new style
38 Select this for sunxi SoCs which uses a DRAM controller like the
39 DesignWare controller used in H3, mainly SoCs after H3, which do
40 not have official open-source DRAM initialization code, but can
41 use modified H3 DRAM initialization code.
44 config SUNXI_DRAM_DW_16BIT
47 Select this for sunxi SoCs with DesignWare DRAM controller and
48 have only 16-bit memory buswidth.
50 config SUNXI_DRAM_DW_32BIT
53 Select this for sunxi SoCs with DesignWare DRAM controller with
54 32-bit memory buswidth.
57 config MACH_SUNXI_H3_H5
62 select SUNXI_DRAM_DW_32BIT
63 select SUNXI_GEN_SUN6I
67 prompt "Sunxi SoC Variant"
71 bool "sun4i (Allwinner A10)"
73 select ARM_CORTEX_CPU_IS_UP
74 select SUNXI_GEN_SUN4I
78 bool "sun5i (Allwinner A13)"
80 select ARM_CORTEX_CPU_IS_UP
81 select SUNXI_GEN_SUN4I
85 bool "sun6i (Allwinner A31)"
87 select CPU_V7_HAS_NONSEC
88 select CPU_V7_HAS_VIRT
89 select ARCH_SUPPORT_PSCI
90 select SUNXI_GEN_SUN6I
92 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
95 bool "sun7i (Allwinner A20)"
97 select CPU_V7_HAS_NONSEC
98 select CPU_V7_HAS_VIRT
99 select ARCH_SUPPORT_PSCI
100 select SUNXI_GEN_SUN4I
102 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
104 config MACH_SUN8I_A23
105 bool "sun8i (Allwinner A23)"
107 select CPU_V7_HAS_NONSEC
108 select CPU_V7_HAS_VIRT
109 select ARCH_SUPPORT_PSCI
110 select SUNXI_GEN_SUN6I
112 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
114 config MACH_SUN8I_A33
115 bool "sun8i (Allwinner A33)"
117 select CPU_V7_HAS_NONSEC
118 select CPU_V7_HAS_VIRT
119 select ARCH_SUPPORT_PSCI
120 select SUNXI_GEN_SUN6I
122 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
124 config MACH_SUN8I_A83T
125 bool "sun8i (Allwinner A83T)"
127 select SUNXI_GEN_SUN6I
131 bool "sun8i (Allwinner H3)"
133 select CPU_V7_HAS_NONSEC
134 select CPU_V7_HAS_VIRT
135 select ARCH_SUPPORT_PSCI
136 select MACH_SUNXI_H3_H5
137 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
139 config MACH_SUN8I_R40
140 bool "sun8i (Allwinner R40)"
142 select CPU_V7_HAS_NONSEC
143 select CPU_V7_HAS_VIRT
144 select ARCH_SUPPORT_PSCI
145 select SUNXI_GEN_SUN6I
148 select SUNXI_DRAM_DW_32BIT
150 config MACH_SUN8I_V3S
151 bool "sun8i (Allwinner V3s)"
153 select CPU_V7_HAS_NONSEC
154 select CPU_V7_HAS_VIRT
155 select ARCH_SUPPORT_PSCI
156 select SUNXI_GEN_SUN6I
158 select SUNXI_DRAM_DW_16BIT
160 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
163 bool "sun9i (Allwinner A80)"
165 select SUNXI_HIGH_SRAM
166 select SUNXI_GEN_SUN6I
170 bool "sun50i (Allwinner A64)"
174 select SUNXI_GEN_SUN6I
175 select SUNXI_HIGH_SRAM
178 select SUNXI_DRAM_DW_32BIT
182 config MACH_SUN50I_H5
183 bool "sun50i (Allwinner H5)"
185 select MACH_SUNXI_H3_H5
186 select SUNXI_HIGH_SRAM
192 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
195 default y if MACH_SUN8I_A23
196 default y if MACH_SUN8I_A33
197 default y if MACH_SUN8I_A83T
198 default y if MACH_SUNXI_H3_H5
199 default y if MACH_SUN8I_R40
200 default y if MACH_SUN8I_V3S
202 config RESERVE_ALLWINNER_BOOT0_HEADER
203 bool "reserve space for Allwinner boot0 header"
204 select ENABLE_ARM_SOC_BOOT0_HOOK
206 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
207 filled with magic values post build. The Allwinner provided boot0
208 blob relies on this information to load and execute U-Boot.
209 Only needed on 64-bit Allwinner boards so far when using boot0.
211 config ARM_BOOT_HOOK_RMR
215 select ENABLE_ARM_SOC_BOOT0_HOOK
217 Insert some ARM32 code at the very beginning of the U-Boot binary
218 which uses an RMR register write to bring the core into AArch64 mode.
219 The very first instruction acts as a switch, since it's carefully
220 chosen to be a NOP in one mode and a branch in the other, so the
221 code would only be executed if not already in AArch64.
222 This allows both the SPL and the U-Boot proper to be entered in
223 either mode and switch to AArch64 if needed.
226 config SUNXI_DRAM_DDR3
229 config SUNXI_DRAM_DDR2
232 config SUNXI_DRAM_LPDDR3
236 prompt "DRAM Type and Timing"
237 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
238 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
240 config SUNXI_DRAM_DDR3_1333
242 select SUNXI_DRAM_DDR3
243 depends on !MACH_SUN8I_V3S
245 This option is the original only supported memory type, which suits
246 many H3/H5/A64 boards available now.
248 config SUNXI_DRAM_LPDDR3_STOCK
249 bool "LPDDR3 with Allwinner stock configuration"
250 select SUNXI_DRAM_LPDDR3
252 This option is the LPDDR3 timing used by the stock boot0 by
255 config SUNXI_DRAM_DDR2_V3S
256 bool "DDR2 found in V3s chip"
257 select SUNXI_DRAM_DDR2
258 depends on MACH_SUN8I_V3S
260 This option is only for the DDR2 memory chip which is co-packaged in
267 int "sunxi dram type"
268 depends on MACH_SUN8I_A83T
271 Set the dram type, 3: DDR3, 7: LPDDR3
274 int "sunxi dram clock speed"
275 default 792 if MACH_SUN9I
276 default 648 if MACH_SUN8I_R40
277 default 312 if MACH_SUN6I || MACH_SUN8I
278 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
280 default 672 if MACH_SUN50I
282 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
283 must be a multiple of 24. For the sun9i (A80), the tested values
284 (for DDR3-1600) are 312 to 792.
286 if MACH_SUN5I || MACH_SUN7I
288 int "sunxi mbus clock speed"
291 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
296 int "sunxi dram zq value"
297 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
298 default 127 if MACH_SUN7I
299 default 14779 if MACH_SUN8I_V3S
300 default 3881979 if MACH_SUN8I_R40
301 default 4145117 if MACH_SUN9I
302 default 3881915 if MACH_SUN50I
304 Set the dram zq value.
307 bool "sunxi dram odt enable"
308 default n if !MACH_SUN8I_A23
309 default y if MACH_SUN8I_A23
310 default y if MACH_SUN8I_R40
311 default y if MACH_SUN50I
313 Select this to enable dram odt (on die termination).
315 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
317 int "sunxi dram emr1 value"
318 default 0 if MACH_SUN4I
319 default 4 if MACH_SUN5I || MACH_SUN7I
321 Set the dram controller emr1 value.
324 hex "sunxi dram tpr3 value"
327 Set the dram controller tpr3 parameter. This parameter configures
328 the delay on the command lane and also phase shifts, which are
329 applied for sampling incoming read data. The default value 0
330 means that no phase/delay adjustments are necessary. Properly
331 configuring this parameter increases reliability at high DRAM
334 config DRAM_DQS_GATING_DELAY
335 hex "sunxi dram dqs_gating_delay value"
338 Set the dram controller dqs_gating_delay parmeter. Each byte
339 encodes the DQS gating delay for each byte lane. The delay
340 granularity is 1/4 cycle. For example, the value 0x05060606
341 means that the delay is 5 quarter-cycles for one lane (1.25
342 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
343 The default value 0 means autodetection. The results of hardware
344 autodetection are not very reliable and depend on the chip
345 temperature (sometimes producing different results on cold start
346 and warm reboot). But the accuracy of hardware autodetection
347 is usually good enough, unless running at really high DRAM
348 clocks speeds (up to 600MHz). If unsure, keep as 0.
351 prompt "sunxi dram timings"
352 default DRAM_TIMINGS_VENDOR_MAGIC
354 Select the timings of the DDR3 chips.
356 config DRAM_TIMINGS_VENDOR_MAGIC
357 bool "Magic vendor timings from Android"
359 The same DRAM timings as in the Allwinner boot0 bootloader.
361 config DRAM_TIMINGS_DDR3_1066F_1333H
362 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
364 Use the timings of the standard JEDEC DDR3-1066F speed bin for
365 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
366 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
367 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
368 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
369 that down binning to DDR3-1066F is supported (because DDR3-1066F
370 uses a bit faster timings than DDR3-1333H).
372 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
373 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
375 Use the timings of the slowest possible JEDEC speed bin for the
376 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
377 DDR3-800E, DDR3-1066G or DDR3-1333J.
384 config DRAM_ODT_CORRECTION
385 int "sunxi dram odt correction value"
388 Set the dram odt correction value (range -255 - 255). In allwinner
389 fex files, this option is found in bits 8-15 of the u32 odt_en variable
390 in the [dram] section. When bit 31 of the odt_en variable is set
391 then the correction is negative. Usually the value for this is 0.
395 default 1008000000 if MACH_SUN4I
396 default 1008000000 if MACH_SUN5I
397 default 1008000000 if MACH_SUN6I
398 default 912000000 if MACH_SUN7I
399 default 1008000000 if MACH_SUN8I
400 default 1008000000 if MACH_SUN9I
401 default 816000000 if MACH_SUN50I
403 config SYS_CONFIG_NAME
404 default "sun4i" if MACH_SUN4I
405 default "sun5i" if MACH_SUN5I
406 default "sun6i" if MACH_SUN6I
407 default "sun7i" if MACH_SUN7I
408 default "sun8i" if MACH_SUN8I
409 default "sun9i" if MACH_SUN9I
410 default "sun50i" if MACH_SUN50I
419 bool "UART0 on MicroSD breakout board"
422 Repurpose the SD card slot for getting access to the UART0 serial
423 console. Primarily useful only for low level u-boot debugging on
424 tablets, where normal UART0 is difficult to access and requires
425 device disassembly and/or soldering. As the SD card can't be used
426 at the same time, the system can be only booted in the FEL mode.
427 Only enable this if you really know what you are doing.
429 config OLD_SUNXI_KERNEL_COMPAT
430 bool "Enable workarounds for booting old kernels"
433 Set this to enable various workarounds for old kernels, this results in
434 sub-optimal settings for newer kernels, only enable if needed.
437 string "MAC power pin"
440 Set the pin used to power the MAC. This takes a string in the format
441 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
444 string "Card detect pin for mmc0"
445 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
448 Set the card detect pin for mmc0, leave empty to not use cd. This
449 takes a string in the format understood by sunxi_name_to_gpio, e.g.
450 PH1 for pin 1 of port H.
453 string "Card detect pin for mmc1"
456 See MMC0_CD_PIN help text.
459 string "Card detect pin for mmc2"
462 See MMC0_CD_PIN help text.
465 string "Card detect pin for mmc3"
468 See MMC0_CD_PIN help text.
471 string "Pins for mmc1"
474 Set the pins used for mmc1, when applicable. This takes a string in the
475 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
478 string "Pins for mmc2"
481 See MMC1_PINS help text.
484 string "Pins for mmc3"
487 See MMC1_PINS help text.
489 config MMC_SUNXI_SLOT_EXTRA
490 int "mmc extra slot number"
493 sunxi builds always enable mmc0, some boards also have a second sdcard
494 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
497 config INITIAL_USB_SCAN_DELAY
498 int "delay initial usb scan by x ms to allow builtin devices to init"
501 Some boards have on board usb devices which need longer than the
502 USB spec's 1 second to connect from board powerup. Set this config
503 option to a non 0 value to add an extra delay before the first usb
507 string "Vbus enable pin for usb0 (otg)"
510 Set the Vbus enable pin for usb0 (otg). This takes a string in the
511 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
514 string "Vbus detect pin for usb0 (otg)"
517 Set the Vbus detect pin for usb0 (otg). This takes a string in the
518 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
521 string "ID detect pin for usb0 (otg)"
524 Set the ID detect pin for usb0 (otg). This takes a string in the
525 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
528 string "Vbus enable pin for usb1 (ehci0)"
529 default "PH6" if MACH_SUN4I || MACH_SUN7I
530 default "PH27" if MACH_SUN6I
532 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
533 a string in the format understood by sunxi_name_to_gpio, e.g.
534 PH1 for pin 1 of port H.
537 string "Vbus enable pin for usb2 (ehci1)"
538 default "PH3" if MACH_SUN4I || MACH_SUN7I
539 default "PH24" if MACH_SUN6I
541 See USB1_VBUS_PIN help text.
544 string "Vbus enable pin for usb3 (ehci2)"
547 See USB1_VBUS_PIN help text.
550 bool "Enable I2C/TWI controller 0"
551 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
552 default n if MACH_SUN6I || MACH_SUN8I
555 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
556 its clock and setting up the bus. This is especially useful on devices
557 with slaves connected to the bus or with pins exposed through e.g. an
558 expansion port/header.
561 bool "Enable I2C/TWI controller 1"
565 See I2C0_ENABLE help text.
568 bool "Enable I2C/TWI controller 2"
572 See I2C0_ENABLE help text.
574 if MACH_SUN6I || MACH_SUN7I
576 bool "Enable I2C/TWI controller 3"
580 See I2C0_ENABLE help text.
585 bool "Enable the PRCM I2C/TWI controller"
586 # This is used for the pmic on H3
587 default y if SY8106A_POWER
590 Set this to y to enable the I2C controller which is part of the PRCM.
595 bool "Enable I2C/TWI controller 4"
599 See I2C0_ENABLE help text.
603 bool "Enable support for gpio-s on axp PMICs"
606 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
609 bool "Enable graphical uboot console on HDMI, LCD or VGA"
610 depends on !MACH_SUN8I_A83T
611 depends on !MACH_SUNXI_H3_H5
612 depends on !MACH_SUN8I_R40
613 depends on !MACH_SUN8I_V3S
614 depends on !MACH_SUN9I
615 depends on !MACH_SUN50I
618 Say Y here to add support for using a cfb console on the HDMI, LCD
619 or VGA output found on most sunxi devices. See doc/README.video for
620 info on how to select the video output and mode.
623 bool "HDMI output support"
624 depends on VIDEO && !MACH_SUN8I
627 Say Y here to add support for outputting video over HDMI.
630 bool "VGA output support"
631 depends on VIDEO && (MACH_SUN4I || MACH_SUN7I)
634 Say Y here to add support for outputting video over VGA.
636 config VIDEO_VGA_VIA_LCD
637 bool "VGA via LCD controller support"
638 depends on VIDEO && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
641 Say Y here to add support for external DACs connected to the parallel
642 LCD interface driving a VGA connector, such as found on the
645 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
646 bool "Force sync active high for VGA via LCD controller support"
647 depends on VIDEO_VGA_VIA_LCD
650 Say Y here if you've a board which uses opendrain drivers for the vga
651 hsync and vsync signals. Opendrain drivers cannot generate steep enough
652 positive edges for a stable video output, so on boards with opendrain
653 drivers the sync signals must always be active high.
655 config VIDEO_VGA_EXTERNAL_DAC_EN
656 string "LCD panel power enable pin"
657 depends on VIDEO_VGA_VIA_LCD
660 Set the enable pin for the external VGA DAC. This takes a string in the
661 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
663 config VIDEO_COMPOSITE
664 bool "Composite video output support"
665 depends on VIDEO && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
668 Say Y here to add support for outputting composite video.
670 config VIDEO_LCD_MODE
671 string "LCD panel timing details"
675 LCD panel timing details string, leave empty if there is no LCD panel.
676 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
677 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
678 Also see: http://linux-sunxi.org/LCD
680 config VIDEO_LCD_DCLK_PHASE
681 int "LCD panel display clock phase"
685 Select LCD panel display clock phase shift, range 0-3.
687 config VIDEO_LCD_POWER
688 string "LCD panel power enable pin"
692 Set the power enable pin for the LCD panel. This takes a string in the
693 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
695 config VIDEO_LCD_RESET
696 string "LCD panel reset pin"
700 Set the reset pin for the LCD panel. This takes a string in the format
701 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
703 config VIDEO_LCD_BL_EN
704 string "LCD panel backlight enable pin"
708 Set the backlight enable pin for the LCD panel. This takes a string in the
709 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
712 config VIDEO_LCD_BL_PWM
713 string "LCD panel backlight pwm pin"
717 Set the backlight pwm pin for the LCD panel. This takes a string in the
718 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
720 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
721 bool "LCD panel backlight pwm is inverted"
725 Set this if the backlight pwm output is active low.
727 config VIDEO_LCD_PANEL_I2C
728 bool "LCD panel needs to be configured via i2c"
733 Say y here if the LCD panel needs to be configured via i2c. This
734 will add a bitbang i2c controller using gpios to talk to the LCD.
736 config VIDEO_LCD_PANEL_I2C_SDA
737 string "LCD panel i2c interface SDA pin"
738 depends on VIDEO_LCD_PANEL_I2C
741 Set the SDA pin for the LCD i2c interface. This takes a string in the
742 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
744 config VIDEO_LCD_PANEL_I2C_SCL
745 string "LCD panel i2c interface SCL pin"
746 depends on VIDEO_LCD_PANEL_I2C
749 Set the SCL pin for the LCD i2c interface. This takes a string in the
750 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
753 # Note only one of these may be selected at a time! But hidden choices are
754 # not supported by Kconfig
755 config VIDEO_LCD_IF_PARALLEL
758 config VIDEO_LCD_IF_LVDS
766 bool "Display Engine 2 video driver"
772 Say y here if you want to build DE2 video driver which is present on
773 newer SoCs. Currently only HDMI output is supported.
777 prompt "LCD panel support"
780 Select which type of LCD panel to support.
782 config VIDEO_LCD_PANEL_PARALLEL
783 bool "Generic parallel interface LCD panel"
784 select VIDEO_LCD_IF_PARALLEL
786 config VIDEO_LCD_PANEL_LVDS
787 bool "Generic lvds interface LCD panel"
788 select VIDEO_LCD_IF_LVDS
790 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
791 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
792 select VIDEO_LCD_SSD2828
793 select VIDEO_LCD_IF_PARALLEL
795 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
797 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
798 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
799 select VIDEO_LCD_ANX9804
800 select VIDEO_LCD_IF_PARALLEL
801 select VIDEO_LCD_PANEL_I2C
803 Select this for eDP LCD panels with 4 lanes running at 1.62G,
804 connected via an ANX9804 bridge chip.
806 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
807 bool "Hitachi tx18d42vm LCD panel"
808 select VIDEO_LCD_HITACHI_TX18D42VM
809 select VIDEO_LCD_IF_LVDS
811 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
813 config VIDEO_LCD_TL059WV5C0
814 bool "tl059wv5c0 LCD panel"
815 select VIDEO_LCD_PANEL_I2C
816 select VIDEO_LCD_IF_PARALLEL
818 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
819 Aigo M60/M608/M606 tablets.
824 string "SATA power pin"
827 Set the pins used to power the SATA. This takes a string in the
828 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
832 int "GMAC Transmit Clock Delay Chain"
835 Set the GMAC Transmit Clock Delay Chain value.
837 config SPL_STACK_R_ADDR
838 default 0x4fe00000 if MACH_SUN4I
839 default 0x4fe00000 if MACH_SUN5I
840 default 0x4fe00000 if MACH_SUN6I
841 default 0x4fe00000 if MACH_SUN7I
842 default 0x4fe00000 if MACH_SUN8I
843 default 0x2fe00000 if MACH_SUN9I
844 default 0x4fe00000 if MACH_SUN50I