4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
33 config DRAM_SUN8I_A83T
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
48 Select this dram controller driver for some sun50i platforms,
52 bool "Allwinner sun6i internal P2WI controller"
54 If you say yes to this option, support will be included for the
55 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
57 The P2WI looks like an SMBus controller (which supports only byte
58 accesses), except that it only supports one slave device.
59 This interface is used to connect to specific PMIC devices (like the
65 Support for the PRCM (Power/Reset/Clock Management) unit available
69 bool "Sunxi AXP PMIC bus access helpers"
71 Select this PMIC bus access helpers for Sunxi platform PRCM or other
72 AXP family PMIC devices.
75 bool "Allwinner sunXi Reduced Serial Bus Driver"
77 Say y here to enable support for Allwinner's Reduced Serial Bus
78 (RSB) support. This controller is responsible for communicating
79 with various RSB based devices, such as AXP223, AXP8XX PMICs,
82 config SUNXI_SRAM_ADDRESS
84 default 0x10000 if MACH_SUN9I || MACH_SUN50I || MACH_SUN50I_H5
85 default 0x20000 if MACH_SUN50I_H6
88 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
89 with the first SRAM region being located at address 0.
90 Some newer SoCs map the boot ROM at address 0 instead and move the
91 SRAM to a different address.
93 config SUNXI_A64_TIMER_ERRATUM
96 # Note only one of these may be selected at a time! But hidden choices are
97 # not supported by Kconfig
98 config SUNXI_GEN_SUN4I
101 Select this for sunxi SoCs which have resets and clocks set up
102 as the original A10 (mach-sun4i).
104 config SUNXI_GEN_SUN6I
107 Select this for sunxi SoCs which have sun6i like periphery, like
108 separate ahb reset control registers, custom pmic bus, new style
114 Select this for sunxi SoCs which uses a DRAM controller like the
115 DesignWare controller used in H3, mainly SoCs after H3, which do
116 not have official open-source DRAM initialization code, but can
117 use modified H3 DRAM initialization code.
120 config SUNXI_DRAM_DW_16BIT
123 Select this for sunxi SoCs with DesignWare DRAM controller and
124 have only 16-bit memory buswidth.
126 config SUNXI_DRAM_DW_32BIT
129 Select this for sunxi SoCs with DesignWare DRAM controller with
130 32-bit memory buswidth.
133 config MACH_SUNXI_H3_H5
139 select SUNXI_DRAM_DW_32BIT
140 select SUNXI_GEN_SUN6I
143 # TODO: try out A80's 8GiB DRAM space
144 config SUNXI_DRAM_MAX_SIZE
146 default 0xC0000000 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN50I_H6
150 prompt "Sunxi SoC Variant"
154 bool "sun4i (Allwinner A10)"
156 select ARM_CORTEX_CPU_IS_UP
157 select DM_SCSI if SCSI
160 select SUNXI_GEN_SUN4I
164 bool "sun5i (Allwinner A13)"
166 select ARM_CORTEX_CPU_IS_UP
169 select SUNXI_GEN_SUN4I
171 imply CONS_INDEX_2 if !DM_SERIAL
174 bool "sun6i (Allwinner A31)"
176 select CPU_V7_HAS_NONSEC
177 select CPU_V7_HAS_VIRT
178 select ARCH_SUPPORT_PSCI
183 select SUNXI_GEN_SUN6I
185 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
188 bool "sun7i (Allwinner A20)"
190 select CPU_V7_HAS_NONSEC
191 select CPU_V7_HAS_VIRT
192 select ARCH_SUPPORT_PSCI
195 select SUNXI_GEN_SUN4I
197 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
199 config MACH_SUN8I_A23
200 bool "sun8i (Allwinner A23)"
202 select CPU_V7_HAS_NONSEC
203 select CPU_V7_HAS_VIRT
204 select ARCH_SUPPORT_PSCI
205 select DRAM_SUN8I_A23
207 select SUNXI_GEN_SUN6I
209 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
210 imply CONS_INDEX_5 if !DM_SERIAL
212 config MACH_SUN8I_A33
213 bool "sun8i (Allwinner A33)"
215 select CPU_V7_HAS_NONSEC
216 select CPU_V7_HAS_VIRT
217 select ARCH_SUPPORT_PSCI
218 select DRAM_SUN8I_A33
220 select SUNXI_GEN_SUN6I
222 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
223 imply CONS_INDEX_5 if !DM_SERIAL
225 config MACH_SUN8I_A83T
226 bool "sun8i (Allwinner A83T)"
228 select DRAM_SUN8I_A83T
230 select SUNXI_GEN_SUN6I
231 select MMC_SUNXI_HAS_NEW_MODE
232 select MMC_SUNXI_HAS_MODE_SWITCH
236 bool "sun8i (Allwinner H3)"
238 select CPU_V7_HAS_NONSEC
239 select CPU_V7_HAS_VIRT
240 select ARCH_SUPPORT_PSCI
241 select MACH_SUNXI_H3_H5
242 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
244 config MACH_SUN8I_R40
245 bool "sun8i (Allwinner R40)"
247 select CPU_V7_HAS_NONSEC
248 select CPU_V7_HAS_VIRT
249 select ARCH_SUPPORT_PSCI
250 select SUNXI_GEN_SUN6I
253 select SUNXI_DRAM_DW_32BIT
255 config MACH_SUN8I_V3S
256 bool "sun8i (Allwinner V3s)"
258 select CPU_V7_HAS_NONSEC
259 select CPU_V7_HAS_VIRT
260 select ARCH_SUPPORT_PSCI
261 select SUNXI_GEN_SUN6I
263 select SUNXI_DRAM_DW_16BIT
265 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
268 bool "sun9i (Allwinner A80)"
272 select SUNXI_GEN_SUN6I
277 bool "sun50i (Allwinner A64)"
283 select SUNXI_GEN_SUN6I
284 select MMC_SUNXI_HAS_NEW_MODE
287 select SUNXI_DRAM_DW_32BIT
290 select SUNXI_A64_TIMER_ERRATUM
292 config MACH_SUN50I_H5
293 bool "sun50i (Allwinner H5)"
295 select MACH_SUNXI_H3_H5
299 config MACH_SUN50I_H6
300 bool "sun50i (Allwinner H6)"
305 select DRAM_SUN50I_H6
309 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
314 default y if MACH_SUN8I_A23
315 default y if MACH_SUN8I_A33
316 default y if MACH_SUN8I_A83T
317 default y if MACH_SUNXI_H3_H5
318 default y if MACH_SUN8I_R40
319 default y if MACH_SUN8I_V3S
321 config RESERVE_ALLWINNER_BOOT0_HEADER
322 bool "reserve space for Allwinner boot0 header"
323 select ENABLE_ARM_SOC_BOOT0_HOOK
325 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
326 filled with magic values post build. The Allwinner provided boot0
327 blob relies on this information to load and execute U-Boot.
328 Only needed on 64-bit Allwinner boards so far when using boot0.
330 config ARM_BOOT_HOOK_RMR
334 select ENABLE_ARM_SOC_BOOT0_HOOK
336 Insert some ARM32 code at the very beginning of the U-Boot binary
337 which uses an RMR register write to bring the core into AArch64 mode.
338 The very first instruction acts as a switch, since it's carefully
339 chosen to be a NOP in one mode and a branch in the other, so the
340 code would only be executed if not already in AArch64.
341 This allows both the SPL and the U-Boot proper to be entered in
342 either mode and switch to AArch64 if needed.
345 config SUNXI_DRAM_DDR3
348 config SUNXI_DRAM_DDR2
351 config SUNXI_DRAM_LPDDR3
355 prompt "DRAM Type and Timing"
356 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
357 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
359 config SUNXI_DRAM_DDR3_1333
361 select SUNXI_DRAM_DDR3
362 depends on !MACH_SUN8I_V3S
364 This option is the original only supported memory type, which suits
365 many H3/H5/A64 boards available now.
367 config SUNXI_DRAM_LPDDR3_STOCK
368 bool "LPDDR3 with Allwinner stock configuration"
369 select SUNXI_DRAM_LPDDR3
371 This option is the LPDDR3 timing used by the stock boot0 by
374 config SUNXI_DRAM_DDR2_V3S
375 bool "DDR2 found in V3s chip"
376 select SUNXI_DRAM_DDR2
377 depends on MACH_SUN8I_V3S
379 This option is only for the DDR2 memory chip which is co-packaged in
386 int "sunxi dram type"
387 depends on MACH_SUN8I_A83T
390 Set the dram type, 3: DDR3, 7: LPDDR3
393 int "sunxi dram clock speed"
394 default 792 if MACH_SUN9I
395 default 648 if MACH_SUN8I_R40
396 default 312 if MACH_SUN6I || MACH_SUN8I
397 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
399 default 672 if MACH_SUN50I
400 default 744 if MACH_SUN50I_H6
402 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
403 must be a multiple of 24. For the sun9i (A80), the tested values
404 (for DDR3-1600) are 312 to 792.
406 if MACH_SUN5I || MACH_SUN7I
408 int "sunxi mbus clock speed"
411 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
416 int "sunxi dram zq value"
417 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
418 default 127 if MACH_SUN7I
419 default 14779 if MACH_SUN8I_V3S
420 default 3881979 if MACH_SUN8I_R40 || MACH_SUN50I_H6
421 default 4145117 if MACH_SUN9I
422 default 3881915 if MACH_SUN50I
424 Set the dram zq value.
427 bool "sunxi dram odt enable"
428 default y if MACH_SUN8I_A23
429 default y if MACH_SUN8I_R40
430 default y if MACH_SUN50I
431 default y if MACH_SUN50I_H6
433 Select this to enable dram odt (on die termination).
435 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
437 int "sunxi dram emr1 value"
438 default 0 if MACH_SUN4I
439 default 4 if MACH_SUN5I || MACH_SUN7I
441 Set the dram controller emr1 value.
444 hex "sunxi dram tpr3 value"
447 Set the dram controller tpr3 parameter. This parameter configures
448 the delay on the command lane and also phase shifts, which are
449 applied for sampling incoming read data. The default value 0
450 means that no phase/delay adjustments are necessary. Properly
451 configuring this parameter increases reliability at high DRAM
454 config DRAM_DQS_GATING_DELAY
455 hex "sunxi dram dqs_gating_delay value"
458 Set the dram controller dqs_gating_delay parmeter. Each byte
459 encodes the DQS gating delay for each byte lane. The delay
460 granularity is 1/4 cycle. For example, the value 0x05060606
461 means that the delay is 5 quarter-cycles for one lane (1.25
462 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
463 The default value 0 means autodetection. The results of hardware
464 autodetection are not very reliable and depend on the chip
465 temperature (sometimes producing different results on cold start
466 and warm reboot). But the accuracy of hardware autodetection
467 is usually good enough, unless running at really high DRAM
468 clocks speeds (up to 600MHz). If unsure, keep as 0.
471 prompt "sunxi dram timings"
472 default DRAM_TIMINGS_VENDOR_MAGIC
474 Select the timings of the DDR3 chips.
476 config DRAM_TIMINGS_VENDOR_MAGIC
477 bool "Magic vendor timings from Android"
479 The same DRAM timings as in the Allwinner boot0 bootloader.
481 config DRAM_TIMINGS_DDR3_1066F_1333H
482 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
484 Use the timings of the standard JEDEC DDR3-1066F speed bin for
485 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
486 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
487 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
488 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
489 that down binning to DDR3-1066F is supported (because DDR3-1066F
490 uses a bit faster timings than DDR3-1333H).
492 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
493 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
495 Use the timings of the slowest possible JEDEC speed bin for the
496 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
497 DDR3-800E, DDR3-1066G or DDR3-1333J.
504 config DRAM_ODT_CORRECTION
505 int "sunxi dram odt correction value"
508 Set the dram odt correction value (range -255 - 255). In allwinner
509 fex files, this option is found in bits 8-15 of the u32 odt_en variable
510 in the [dram] section. When bit 31 of the odt_en variable is set
511 then the correction is negative. Usually the value for this is 0.
515 default 1008000000 if MACH_SUN4I
516 default 1008000000 if MACH_SUN5I
517 default 1008000000 if MACH_SUN6I
518 default 912000000 if MACH_SUN7I
519 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
520 default 1008000000 if MACH_SUN8I
521 default 1008000000 if MACH_SUN9I
522 default 888000000 if MACH_SUN50I_H6
524 config SYS_CONFIG_NAME
525 default "sun4i" if MACH_SUN4I
526 default "sun5i" if MACH_SUN5I
527 default "sun6i" if MACH_SUN6I
528 default "sun7i" if MACH_SUN7I
529 default "sun8i" if MACH_SUN8I
530 default "sun9i" if MACH_SUN9I
531 default "sun50i" if MACH_SUN50I
532 default "sun50i" if MACH_SUN50I_H6
541 bool "UART0 on MicroSD breakout board"
544 Repurpose the SD card slot for getting access to the UART0 serial
545 console. Primarily useful only for low level u-boot debugging on
546 tablets, where normal UART0 is difficult to access and requires
547 device disassembly and/or soldering. As the SD card can't be used
548 at the same time, the system can be only booted in the FEL mode.
549 Only enable this if you really know what you are doing.
551 config OLD_SUNXI_KERNEL_COMPAT
552 bool "Enable workarounds for booting old kernels"
555 Set this to enable various workarounds for old kernels, this results in
556 sub-optimal settings for newer kernels, only enable if needed.
559 string "MAC power pin"
562 Set the pin used to power the MAC. This takes a string in the format
563 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
566 string "Card detect pin for mmc0"
567 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
570 Set the card detect pin for mmc0, leave empty to not use cd. This
571 takes a string in the format understood by sunxi_name_to_gpio, e.g.
572 PH1 for pin 1 of port H.
575 string "Card detect pin for mmc1"
578 See MMC0_CD_PIN help text.
581 string "Card detect pin for mmc2"
584 See MMC0_CD_PIN help text.
587 string "Card detect pin for mmc3"
590 See MMC0_CD_PIN help text.
593 string "Pins for mmc1"
596 Set the pins used for mmc1, when applicable. This takes a string in the
597 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
600 string "Pins for mmc2"
603 See MMC1_PINS help text.
606 string "Pins for mmc3"
609 See MMC1_PINS help text.
611 config MMC_SUNXI_SLOT_EXTRA
612 int "mmc extra slot number"
615 sunxi builds always enable mmc0, some boards also have a second sdcard
616 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
619 config INITIAL_USB_SCAN_DELAY
620 int "delay initial usb scan by x ms to allow builtin devices to init"
623 Some boards have on board usb devices which need longer than the
624 USB spec's 1 second to connect from board powerup. Set this config
625 option to a non 0 value to add an extra delay before the first usb
629 string "Vbus enable pin for usb0 (otg)"
632 Set the Vbus enable pin for usb0 (otg). This takes a string in the
633 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
636 string "Vbus detect pin for usb0 (otg)"
639 Set the Vbus detect pin for usb0 (otg). This takes a string in the
640 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
643 string "ID detect pin for usb0 (otg)"
646 Set the ID detect pin for usb0 (otg). This takes a string in the
647 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
650 string "Vbus enable pin for usb1 (ehci0)"
651 default "PH6" if MACH_SUN4I || MACH_SUN7I
652 default "PH27" if MACH_SUN6I
654 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
655 a string in the format understood by sunxi_name_to_gpio, e.g.
656 PH1 for pin 1 of port H.
659 string "Vbus enable pin for usb2 (ehci1)"
660 default "PH3" if MACH_SUN4I || MACH_SUN7I
661 default "PH24" if MACH_SUN6I
663 See USB1_VBUS_PIN help text.
666 string "Vbus enable pin for usb3 (ehci2)"
669 See USB1_VBUS_PIN help text.
672 bool "Enable I2C/TWI controller 0"
673 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
674 default n if MACH_SUN6I || MACH_SUN8I
677 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
678 its clock and setting up the bus. This is especially useful on devices
679 with slaves connected to the bus or with pins exposed through e.g. an
680 expansion port/header.
683 bool "Enable I2C/TWI controller 1"
687 See I2C0_ENABLE help text.
690 bool "Enable I2C/TWI controller 2"
694 See I2C0_ENABLE help text.
696 if MACH_SUN6I || MACH_SUN7I
698 bool "Enable I2C/TWI controller 3"
702 See I2C0_ENABLE help text.
707 bool "Enable the PRCM I2C/TWI controller"
708 # This is used for the pmic on H3
709 default y if SY8106A_POWER
712 Set this to y to enable the I2C controller which is part of the PRCM.
717 bool "Enable I2C/TWI controller 4"
721 See I2C0_ENABLE help text.
725 bool "Enable support for gpio-s on axp PMICs"
728 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
731 bool "Enable graphical uboot console on HDMI, LCD or VGA"
732 depends on !MACH_SUN8I_A83T
733 depends on !MACH_SUNXI_H3_H5
734 depends on !MACH_SUN8I_R40
735 depends on !MACH_SUN8I_V3S
736 depends on !MACH_SUN9I
737 depends on !MACH_SUN50I
738 depends on !MACH_SUN50I_H6
740 imply VIDEO_DT_SIMPLEFB
743 Say Y here to add support for using a cfb console on the HDMI, LCD
744 or VGA output found on most sunxi devices. See doc/README.video for
745 info on how to select the video output and mode.
748 bool "HDMI output support"
749 depends on VIDEO_SUNXI && !MACH_SUN8I
752 Say Y here to add support for outputting video over HDMI.
755 bool "VGA output support"
756 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
759 Say Y here to add support for outputting video over VGA.
761 config VIDEO_VGA_VIA_LCD
762 bool "VGA via LCD controller support"
763 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
766 Say Y here to add support for external DACs connected to the parallel
767 LCD interface driving a VGA connector, such as found on the
770 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
771 bool "Force sync active high for VGA via LCD controller support"
772 depends on VIDEO_VGA_VIA_LCD
775 Say Y here if you've a board which uses opendrain drivers for the vga
776 hsync and vsync signals. Opendrain drivers cannot generate steep enough
777 positive edges for a stable video output, so on boards with opendrain
778 drivers the sync signals must always be active high.
780 config VIDEO_VGA_EXTERNAL_DAC_EN
781 string "LCD panel power enable pin"
782 depends on VIDEO_VGA_VIA_LCD
785 Set the enable pin for the external VGA DAC. This takes a string in the
786 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
788 config VIDEO_COMPOSITE
789 bool "Composite video output support"
790 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
793 Say Y here to add support for outputting composite video.
795 config VIDEO_LCD_MODE
796 string "LCD panel timing details"
797 depends on VIDEO_SUNXI
800 LCD panel timing details string, leave empty if there is no LCD panel.
801 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
802 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
803 Also see: http://linux-sunxi.org/LCD
805 config VIDEO_LCD_DCLK_PHASE
806 int "LCD panel display clock phase"
807 depends on VIDEO_SUNXI || DM_VIDEO
810 Select LCD panel display clock phase shift, range 0-3.
812 config VIDEO_LCD_POWER
813 string "LCD panel power enable pin"
814 depends on VIDEO_SUNXI
817 Set the power enable pin for the LCD panel. This takes a string in the
818 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
820 config VIDEO_LCD_RESET
821 string "LCD panel reset pin"
822 depends on VIDEO_SUNXI
825 Set the reset pin for the LCD panel. This takes a string in the format
826 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
828 config VIDEO_LCD_BL_EN
829 string "LCD panel backlight enable pin"
830 depends on VIDEO_SUNXI
833 Set the backlight enable pin for the LCD panel. This takes a string in the
834 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
837 config VIDEO_LCD_BL_PWM
838 string "LCD panel backlight pwm pin"
839 depends on VIDEO_SUNXI
842 Set the backlight pwm pin for the LCD panel. This takes a string in the
843 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
845 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
846 bool "LCD panel backlight pwm is inverted"
847 depends on VIDEO_SUNXI
850 Set this if the backlight pwm output is active low.
852 config VIDEO_LCD_PANEL_I2C
853 bool "LCD panel needs to be configured via i2c"
854 depends on VIDEO_SUNXI
858 Say y here if the LCD panel needs to be configured via i2c. This
859 will add a bitbang i2c controller using gpios to talk to the LCD.
861 config VIDEO_LCD_PANEL_I2C_SDA
862 string "LCD panel i2c interface SDA pin"
863 depends on VIDEO_LCD_PANEL_I2C
866 Set the SDA pin for the LCD i2c interface. This takes a string in the
867 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
869 config VIDEO_LCD_PANEL_I2C_SCL
870 string "LCD panel i2c interface SCL pin"
871 depends on VIDEO_LCD_PANEL_I2C
874 Set the SCL pin for the LCD i2c interface. This takes a string in the
875 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
878 # Note only one of these may be selected at a time! But hidden choices are
879 # not supported by Kconfig
880 config VIDEO_LCD_IF_PARALLEL
883 config VIDEO_LCD_IF_LVDS
891 bool "Display Engine 2 video driver"
895 imply VIDEO_DT_SIMPLEFB
898 Say y here if you want to build DE2 video driver which is present on
899 newer SoCs. Currently only HDMI output is supported.
903 prompt "LCD panel support"
904 depends on VIDEO_SUNXI
906 Select which type of LCD panel to support.
908 config VIDEO_LCD_PANEL_PARALLEL
909 bool "Generic parallel interface LCD panel"
910 select VIDEO_LCD_IF_PARALLEL
912 config VIDEO_LCD_PANEL_LVDS
913 bool "Generic lvds interface LCD panel"
914 select VIDEO_LCD_IF_LVDS
916 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
917 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
918 select VIDEO_LCD_SSD2828
919 select VIDEO_LCD_IF_PARALLEL
921 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
923 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
924 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
925 select VIDEO_LCD_ANX9804
926 select VIDEO_LCD_IF_PARALLEL
927 select VIDEO_LCD_PANEL_I2C
929 Select this for eDP LCD panels with 4 lanes running at 1.62G,
930 connected via an ANX9804 bridge chip.
932 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
933 bool "Hitachi tx18d42vm LCD panel"
934 select VIDEO_LCD_HITACHI_TX18D42VM
935 select VIDEO_LCD_IF_LVDS
937 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
939 config VIDEO_LCD_TL059WV5C0
940 bool "tl059wv5c0 LCD panel"
941 select VIDEO_LCD_PANEL_I2C
942 select VIDEO_LCD_IF_PARALLEL
944 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
945 Aigo M60/M608/M606 tablets.
950 string "SATA power pin"
953 Set the pins used to power the SATA. This takes a string in the
954 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
958 int "GMAC Transmit Clock Delay Chain"
961 Set the GMAC Transmit Clock Delay Chain value.
963 config SPL_STACK_R_ADDR
964 default 0x4fe00000 if MACH_SUN4I
965 default 0x4fe00000 if MACH_SUN5I
966 default 0x4fe00000 if MACH_SUN6I
967 default 0x4fe00000 if MACH_SUN7I
968 default 0x4fe00000 if MACH_SUN8I
969 default 0x2fe00000 if MACH_SUN9I
970 default 0x4fe00000 if MACH_SUN50I
971 default 0x4fe00000 if MACH_SUN50I_H6
974 bool "Support for SPI Flash on Allwinner SoCs in SPL"
975 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
977 Enable support for SPI Flash. This option allows SPL to read from
978 sunxi SPI Flash. It uses the same method as the boot ROM, so does
979 not need any extra configuration.
981 config PINE64_DT_SELECTION
982 bool "Enable Pine64 device tree selection code"
983 depends on MACH_SUN50I
985 The original Pine A64 and Pine A64+ are similar but different
986 boards and can be differed by the DRAM size. Pine A64 has
987 512MiB DRAM, and Pine A64+ has 1GiB or 2GiB. By selecting this
988 option, the device tree selection code specific to Pine64 which
989 utilizes the DRAM size will be enabled.