4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
33 config DRAM_SUN8I_A83T
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
46 bool "Allwinner sun6i internal P2WI controller"
48 If you say yes to this option, support will be included for the
49 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
51 The P2WI looks like an SMBus controller (which supports only byte
52 accesses), except that it only supports one slave device.
53 This interface is used to connect to specific PMIC devices (like the
59 Support for the PRCM (Power/Reset/Clock Management) unit available
63 bool "Sunxi AXP PMIC bus access helpers"
65 Select this PMIC bus access helpers for Sunxi platform PRCM or other
66 AXP family PMIC devices.
69 bool "Allwinner sunXi Reduced Serial Bus Driver"
71 Say y here to enable support for Allwinner's Reduced Serial Bus
72 (RSB) support. This controller is responsible for communicating
73 with various RSB based devices, such as AXP223, AXP8XX PMICs,
76 config SUNXI_HIGH_SRAM
80 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
81 with the first SRAM region being located at address 0.
82 Some newer SoCs map the boot ROM at address 0 instead and move the
83 SRAM to 64KB, just behind the mask ROM.
84 Chips using the latter setup are supposed to select this option to
85 adjust the addresses accordingly.
87 config SUNXI_A64_TIMER_ERRATUM
90 # Note only one of these may be selected at a time! But hidden choices are
91 # not supported by Kconfig
92 config SUNXI_GEN_SUN4I
95 Select this for sunxi SoCs which have resets and clocks set up
96 as the original A10 (mach-sun4i).
98 config SUNXI_GEN_SUN6I
101 Select this for sunxi SoCs which have sun6i like periphery, like
102 separate ahb reset control registers, custom pmic bus, new style
108 Select this for sunxi SoCs which uses a DRAM controller like the
109 DesignWare controller used in H3, mainly SoCs after H3, which do
110 not have official open-source DRAM initialization code, but can
111 use modified H3 DRAM initialization code.
114 config SUNXI_DRAM_DW_16BIT
117 Select this for sunxi SoCs with DesignWare DRAM controller and
118 have only 16-bit memory buswidth.
120 config SUNXI_DRAM_DW_32BIT
123 Select this for sunxi SoCs with DesignWare DRAM controller with
124 32-bit memory buswidth.
127 config MACH_SUNXI_H3_H5
133 select SUNXI_DRAM_DW_32BIT
134 select SUNXI_GEN_SUN6I
138 prompt "Sunxi SoC Variant"
142 bool "sun4i (Allwinner A10)"
144 select ARM_CORTEX_CPU_IS_UP
147 select SUNXI_GEN_SUN4I
151 bool "sun5i (Allwinner A13)"
153 select ARM_CORTEX_CPU_IS_UP
156 select SUNXI_GEN_SUN4I
158 imply CONS_INDEX_2 if !DM_SERIAL
161 bool "sun6i (Allwinner A31)"
163 select CPU_V7_HAS_NONSEC
164 select CPU_V7_HAS_VIRT
165 select ARCH_SUPPORT_PSCI
170 select SUNXI_GEN_SUN6I
172 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
175 bool "sun7i (Allwinner A20)"
177 select CPU_V7_HAS_NONSEC
178 select CPU_V7_HAS_VIRT
179 select ARCH_SUPPORT_PSCI
182 select SUNXI_GEN_SUN4I
184 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
186 config MACH_SUN8I_A23
187 bool "sun8i (Allwinner A23)"
189 select CPU_V7_HAS_NONSEC
190 select CPU_V7_HAS_VIRT
191 select ARCH_SUPPORT_PSCI
192 select DRAM_SUN8I_A23
194 select SUNXI_GEN_SUN6I
196 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
197 imply CONS_INDEX_5 if !DM_SERIAL
199 config MACH_SUN8I_A33
200 bool "sun8i (Allwinner A33)"
202 select CPU_V7_HAS_NONSEC
203 select CPU_V7_HAS_VIRT
204 select ARCH_SUPPORT_PSCI
205 select DRAM_SUN8I_A33
207 select SUNXI_GEN_SUN6I
209 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
210 imply CONS_INDEX_5 if !DM_SERIAL
212 config MACH_SUN8I_A83T
213 bool "sun8i (Allwinner A83T)"
215 select DRAM_SUN8I_A83T
217 select SUNXI_GEN_SUN6I
218 select MMC_SUNXI_HAS_NEW_MODE
222 bool "sun8i (Allwinner H3)"
224 select CPU_V7_HAS_NONSEC
225 select CPU_V7_HAS_VIRT
226 select ARCH_SUPPORT_PSCI
227 select MACH_SUNXI_H3_H5
228 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
230 config MACH_SUN8I_R40
231 bool "sun8i (Allwinner R40)"
233 select CPU_V7_HAS_NONSEC
234 select CPU_V7_HAS_VIRT
235 select ARCH_SUPPORT_PSCI
236 select SUNXI_GEN_SUN6I
239 select SUNXI_DRAM_DW_32BIT
241 config MACH_SUN8I_V3S
242 bool "sun8i (Allwinner V3s)"
244 select CPU_V7_HAS_NONSEC
245 select CPU_V7_HAS_VIRT
246 select ARCH_SUPPORT_PSCI
247 select SUNXI_GEN_SUN6I
249 select SUNXI_DRAM_DW_16BIT
251 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
254 bool "sun9i (Allwinner A80)"
258 select SUNXI_HIGH_SRAM
259 select SUNXI_GEN_SUN6I
264 bool "sun50i (Allwinner A64)"
269 select SUNXI_GEN_SUN6I
270 select SUNXI_HIGH_SRAM
273 select SUNXI_DRAM_DW_32BIT
276 select SUNXI_A64_TIMER_ERRATUM
278 config MACH_SUN50I_H5
279 bool "sun50i (Allwinner H5)"
281 select MACH_SUNXI_H3_H5
282 select SUNXI_HIGH_SRAM
288 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
293 default y if MACH_SUN8I_A23
294 default y if MACH_SUN8I_A33
295 default y if MACH_SUN8I_A83T
296 default y if MACH_SUNXI_H3_H5
297 default y if MACH_SUN8I_R40
298 default y if MACH_SUN8I_V3S
300 config RESERVE_ALLWINNER_BOOT0_HEADER
301 bool "reserve space for Allwinner boot0 header"
302 select ENABLE_ARM_SOC_BOOT0_HOOK
304 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
305 filled with magic values post build. The Allwinner provided boot0
306 blob relies on this information to load and execute U-Boot.
307 Only needed on 64-bit Allwinner boards so far when using boot0.
309 config ARM_BOOT_HOOK_RMR
313 select ENABLE_ARM_SOC_BOOT0_HOOK
315 Insert some ARM32 code at the very beginning of the U-Boot binary
316 which uses an RMR register write to bring the core into AArch64 mode.
317 The very first instruction acts as a switch, since it's carefully
318 chosen to be a NOP in one mode and a branch in the other, so the
319 code would only be executed if not already in AArch64.
320 This allows both the SPL and the U-Boot proper to be entered in
321 either mode and switch to AArch64 if needed.
324 config SUNXI_DRAM_DDR3
327 config SUNXI_DRAM_DDR2
330 config SUNXI_DRAM_LPDDR3
334 prompt "DRAM Type and Timing"
335 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
336 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
338 config SUNXI_DRAM_DDR3_1333
340 select SUNXI_DRAM_DDR3
341 depends on !MACH_SUN8I_V3S
343 This option is the original only supported memory type, which suits
344 many H3/H5/A64 boards available now.
346 config SUNXI_DRAM_LPDDR3_STOCK
347 bool "LPDDR3 with Allwinner stock configuration"
348 select SUNXI_DRAM_LPDDR3
350 This option is the LPDDR3 timing used by the stock boot0 by
353 config SUNXI_DRAM_DDR2_V3S
354 bool "DDR2 found in V3s chip"
355 select SUNXI_DRAM_DDR2
356 depends on MACH_SUN8I_V3S
358 This option is only for the DDR2 memory chip which is co-packaged in
365 int "sunxi dram type"
366 depends on MACH_SUN8I_A83T
369 Set the dram type, 3: DDR3, 7: LPDDR3
372 int "sunxi dram clock speed"
373 default 792 if MACH_SUN9I
374 default 648 if MACH_SUN8I_R40
375 default 312 if MACH_SUN6I || MACH_SUN8I
376 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
378 default 672 if MACH_SUN50I
380 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
381 must be a multiple of 24. For the sun9i (A80), the tested values
382 (for DDR3-1600) are 312 to 792.
384 if MACH_SUN5I || MACH_SUN7I
386 int "sunxi mbus clock speed"
389 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
394 int "sunxi dram zq value"
395 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
396 default 127 if MACH_SUN7I
397 default 14779 if MACH_SUN8I_V3S
398 default 3881979 if MACH_SUN8I_R40
399 default 4145117 if MACH_SUN9I
400 default 3881915 if MACH_SUN50I
402 Set the dram zq value.
405 bool "sunxi dram odt enable"
406 default n if !MACH_SUN8I_A23
407 default y if MACH_SUN8I_A23
408 default y if MACH_SUN8I_R40
409 default y if MACH_SUN50I
411 Select this to enable dram odt (on die termination).
413 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
415 int "sunxi dram emr1 value"
416 default 0 if MACH_SUN4I
417 default 4 if MACH_SUN5I || MACH_SUN7I
419 Set the dram controller emr1 value.
422 hex "sunxi dram tpr3 value"
425 Set the dram controller tpr3 parameter. This parameter configures
426 the delay on the command lane and also phase shifts, which are
427 applied for sampling incoming read data. The default value 0
428 means that no phase/delay adjustments are necessary. Properly
429 configuring this parameter increases reliability at high DRAM
432 config DRAM_DQS_GATING_DELAY
433 hex "sunxi dram dqs_gating_delay value"
436 Set the dram controller dqs_gating_delay parmeter. Each byte
437 encodes the DQS gating delay for each byte lane. The delay
438 granularity is 1/4 cycle. For example, the value 0x05060606
439 means that the delay is 5 quarter-cycles for one lane (1.25
440 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
441 The default value 0 means autodetection. The results of hardware
442 autodetection are not very reliable and depend on the chip
443 temperature (sometimes producing different results on cold start
444 and warm reboot). But the accuracy of hardware autodetection
445 is usually good enough, unless running at really high DRAM
446 clocks speeds (up to 600MHz). If unsure, keep as 0.
449 prompt "sunxi dram timings"
450 default DRAM_TIMINGS_VENDOR_MAGIC
452 Select the timings of the DDR3 chips.
454 config DRAM_TIMINGS_VENDOR_MAGIC
455 bool "Magic vendor timings from Android"
457 The same DRAM timings as in the Allwinner boot0 bootloader.
459 config DRAM_TIMINGS_DDR3_1066F_1333H
460 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
462 Use the timings of the standard JEDEC DDR3-1066F speed bin for
463 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
464 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
465 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
466 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
467 that down binning to DDR3-1066F is supported (because DDR3-1066F
468 uses a bit faster timings than DDR3-1333H).
470 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
471 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
473 Use the timings of the slowest possible JEDEC speed bin for the
474 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
475 DDR3-800E, DDR3-1066G or DDR3-1333J.
482 config DRAM_ODT_CORRECTION
483 int "sunxi dram odt correction value"
486 Set the dram odt correction value (range -255 - 255). In allwinner
487 fex files, this option is found in bits 8-15 of the u32 odt_en variable
488 in the [dram] section. When bit 31 of the odt_en variable is set
489 then the correction is negative. Usually the value for this is 0.
493 default 1008000000 if MACH_SUN4I
494 default 1008000000 if MACH_SUN5I
495 default 1008000000 if MACH_SUN6I
496 default 912000000 if MACH_SUN7I
497 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
498 default 1008000000 if MACH_SUN8I
499 default 1008000000 if MACH_SUN9I
501 config SYS_CONFIG_NAME
502 default "sun4i" if MACH_SUN4I
503 default "sun5i" if MACH_SUN5I
504 default "sun6i" if MACH_SUN6I
505 default "sun7i" if MACH_SUN7I
506 default "sun8i" if MACH_SUN8I
507 default "sun9i" if MACH_SUN9I
508 default "sun50i" if MACH_SUN50I
517 bool "UART0 on MicroSD breakout board"
520 Repurpose the SD card slot for getting access to the UART0 serial
521 console. Primarily useful only for low level u-boot debugging on
522 tablets, where normal UART0 is difficult to access and requires
523 device disassembly and/or soldering. As the SD card can't be used
524 at the same time, the system can be only booted in the FEL mode.
525 Only enable this if you really know what you are doing.
527 config OLD_SUNXI_KERNEL_COMPAT
528 bool "Enable workarounds for booting old kernels"
531 Set this to enable various workarounds for old kernels, this results in
532 sub-optimal settings for newer kernels, only enable if needed.
535 string "MAC power pin"
538 Set the pin used to power the MAC. This takes a string in the format
539 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
542 string "Card detect pin for mmc0"
543 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
546 Set the card detect pin for mmc0, leave empty to not use cd. This
547 takes a string in the format understood by sunxi_name_to_gpio, e.g.
548 PH1 for pin 1 of port H.
551 string "Card detect pin for mmc1"
554 See MMC0_CD_PIN help text.
557 string "Card detect pin for mmc2"
560 See MMC0_CD_PIN help text.
563 string "Card detect pin for mmc3"
566 See MMC0_CD_PIN help text.
569 string "Pins for mmc1"
572 Set the pins used for mmc1, when applicable. This takes a string in the
573 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
576 string "Pins for mmc2"
579 See MMC1_PINS help text.
582 string "Pins for mmc3"
585 See MMC1_PINS help text.
587 config MMC_SUNXI_SLOT_EXTRA
588 int "mmc extra slot number"
591 sunxi builds always enable mmc0, some boards also have a second sdcard
592 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
595 config INITIAL_USB_SCAN_DELAY
596 int "delay initial usb scan by x ms to allow builtin devices to init"
599 Some boards have on board usb devices which need longer than the
600 USB spec's 1 second to connect from board powerup. Set this config
601 option to a non 0 value to add an extra delay before the first usb
605 string "Vbus enable pin for usb0 (otg)"
608 Set the Vbus enable pin for usb0 (otg). This takes a string in the
609 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
612 string "Vbus detect pin for usb0 (otg)"
615 Set the Vbus detect pin for usb0 (otg). This takes a string in the
616 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
619 string "ID detect pin for usb0 (otg)"
622 Set the ID detect pin for usb0 (otg). This takes a string in the
623 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
626 string "Vbus enable pin for usb1 (ehci0)"
627 default "PH6" if MACH_SUN4I || MACH_SUN7I
628 default "PH27" if MACH_SUN6I
630 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
631 a string in the format understood by sunxi_name_to_gpio, e.g.
632 PH1 for pin 1 of port H.
635 string "Vbus enable pin for usb2 (ehci1)"
636 default "PH3" if MACH_SUN4I || MACH_SUN7I
637 default "PH24" if MACH_SUN6I
639 See USB1_VBUS_PIN help text.
642 string "Vbus enable pin for usb3 (ehci2)"
645 See USB1_VBUS_PIN help text.
648 bool "Enable I2C/TWI controller 0"
649 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
650 default n if MACH_SUN6I || MACH_SUN8I
653 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
654 its clock and setting up the bus. This is especially useful on devices
655 with slaves connected to the bus or with pins exposed through e.g. an
656 expansion port/header.
659 bool "Enable I2C/TWI controller 1"
663 See I2C0_ENABLE help text.
666 bool "Enable I2C/TWI controller 2"
670 See I2C0_ENABLE help text.
672 if MACH_SUN6I || MACH_SUN7I
674 bool "Enable I2C/TWI controller 3"
678 See I2C0_ENABLE help text.
683 bool "Enable the PRCM I2C/TWI controller"
684 # This is used for the pmic on H3
685 default y if SY8106A_POWER
688 Set this to y to enable the I2C controller which is part of the PRCM.
693 bool "Enable I2C/TWI controller 4"
697 See I2C0_ENABLE help text.
701 bool "Enable support for gpio-s on axp PMICs"
704 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
707 bool "Enable graphical uboot console on HDMI, LCD or VGA"
708 depends on !MACH_SUN8I_A83T
709 depends on !MACH_SUNXI_H3_H5
710 depends on !MACH_SUN8I_R40
711 depends on !MACH_SUN8I_V3S
712 depends on !MACH_SUN9I
713 depends on !MACH_SUN50I
715 imply VIDEO_DT_SIMPLEFB
718 Say Y here to add support for using a cfb console on the HDMI, LCD
719 or VGA output found on most sunxi devices. See doc/README.video for
720 info on how to select the video output and mode.
723 bool "HDMI output support"
724 depends on VIDEO_SUNXI && !MACH_SUN8I
727 Say Y here to add support for outputting video over HDMI.
730 bool "VGA output support"
731 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
734 Say Y here to add support for outputting video over VGA.
736 config VIDEO_VGA_VIA_LCD
737 bool "VGA via LCD controller support"
738 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
741 Say Y here to add support for external DACs connected to the parallel
742 LCD interface driving a VGA connector, such as found on the
745 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
746 bool "Force sync active high for VGA via LCD controller support"
747 depends on VIDEO_VGA_VIA_LCD
750 Say Y here if you've a board which uses opendrain drivers for the vga
751 hsync and vsync signals. Opendrain drivers cannot generate steep enough
752 positive edges for a stable video output, so on boards with opendrain
753 drivers the sync signals must always be active high.
755 config VIDEO_VGA_EXTERNAL_DAC_EN
756 string "LCD panel power enable pin"
757 depends on VIDEO_VGA_VIA_LCD
760 Set the enable pin for the external VGA DAC. This takes a string in the
761 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
763 config VIDEO_COMPOSITE
764 bool "Composite video output support"
765 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
768 Say Y here to add support for outputting composite video.
770 config VIDEO_LCD_MODE
771 string "LCD panel timing details"
772 depends on VIDEO_SUNXI
775 LCD panel timing details string, leave empty if there is no LCD panel.
776 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
777 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
778 Also see: http://linux-sunxi.org/LCD
780 config VIDEO_LCD_DCLK_PHASE
781 int "LCD panel display clock phase"
782 depends on VIDEO_SUNXI || DM_VIDEO
785 Select LCD panel display clock phase shift, range 0-3.
787 config VIDEO_LCD_POWER
788 string "LCD panel power enable pin"
789 depends on VIDEO_SUNXI
792 Set the power enable pin for the LCD panel. This takes a string in the
793 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
795 config VIDEO_LCD_RESET
796 string "LCD panel reset pin"
797 depends on VIDEO_SUNXI
800 Set the reset pin for the LCD panel. This takes a string in the format
801 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
803 config VIDEO_LCD_BL_EN
804 string "LCD panel backlight enable pin"
805 depends on VIDEO_SUNXI
808 Set the backlight enable pin for the LCD panel. This takes a string in the
809 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
812 config VIDEO_LCD_BL_PWM
813 string "LCD panel backlight pwm pin"
814 depends on VIDEO_SUNXI
817 Set the backlight pwm pin for the LCD panel. This takes a string in the
818 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
820 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
821 bool "LCD panel backlight pwm is inverted"
822 depends on VIDEO_SUNXI
825 Set this if the backlight pwm output is active low.
827 config VIDEO_LCD_PANEL_I2C
828 bool "LCD panel needs to be configured via i2c"
829 depends on VIDEO_SUNXI
833 Say y here if the LCD panel needs to be configured via i2c. This
834 will add a bitbang i2c controller using gpios to talk to the LCD.
836 config VIDEO_LCD_PANEL_I2C_SDA
837 string "LCD panel i2c interface SDA pin"
838 depends on VIDEO_LCD_PANEL_I2C
841 Set the SDA pin for the LCD i2c interface. This takes a string in the
842 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
844 config VIDEO_LCD_PANEL_I2C_SCL
845 string "LCD panel i2c interface SCL pin"
846 depends on VIDEO_LCD_PANEL_I2C
849 Set the SCL pin for the LCD i2c interface. This takes a string in the
850 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
853 # Note only one of these may be selected at a time! But hidden choices are
854 # not supported by Kconfig
855 config VIDEO_LCD_IF_PARALLEL
858 config VIDEO_LCD_IF_LVDS
866 bool "Display Engine 2 video driver"
870 imply VIDEO_DT_SIMPLEFB
873 Say y here if you want to build DE2 video driver which is present on
874 newer SoCs. Currently only HDMI output is supported.
878 prompt "LCD panel support"
879 depends on VIDEO_SUNXI
881 Select which type of LCD panel to support.
883 config VIDEO_LCD_PANEL_PARALLEL
884 bool "Generic parallel interface LCD panel"
885 select VIDEO_LCD_IF_PARALLEL
887 config VIDEO_LCD_PANEL_LVDS
888 bool "Generic lvds interface LCD panel"
889 select VIDEO_LCD_IF_LVDS
891 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
892 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
893 select VIDEO_LCD_SSD2828
894 select VIDEO_LCD_IF_PARALLEL
896 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
898 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
899 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
900 select VIDEO_LCD_ANX9804
901 select VIDEO_LCD_IF_PARALLEL
902 select VIDEO_LCD_PANEL_I2C
904 Select this for eDP LCD panels with 4 lanes running at 1.62G,
905 connected via an ANX9804 bridge chip.
907 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
908 bool "Hitachi tx18d42vm LCD panel"
909 select VIDEO_LCD_HITACHI_TX18D42VM
910 select VIDEO_LCD_IF_LVDS
912 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
914 config VIDEO_LCD_TL059WV5C0
915 bool "tl059wv5c0 LCD panel"
916 select VIDEO_LCD_PANEL_I2C
917 select VIDEO_LCD_IF_PARALLEL
919 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
920 Aigo M60/M608/M606 tablets.
925 string "SATA power pin"
928 Set the pins used to power the SATA. This takes a string in the
929 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
933 int "GMAC Transmit Clock Delay Chain"
936 Set the GMAC Transmit Clock Delay Chain value.
938 config SPL_STACK_R_ADDR
939 default 0x4fe00000 if MACH_SUN4I
940 default 0x4fe00000 if MACH_SUN5I
941 default 0x4fe00000 if MACH_SUN6I
942 default 0x4fe00000 if MACH_SUN7I
943 default 0x4fe00000 if MACH_SUN8I
944 default 0x2fe00000 if MACH_SUN9I
945 default 0x4fe00000 if MACH_SUN50I
948 bool "Support for SPI Flash on Allwinner SoCs in SPL"
949 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
951 Enable support for SPI Flash. This option allows SPL to read from
952 sunxi SPI Flash. It uses the same method as the boot ROM, so does
953 not need any extra configuration.