4 default "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" if !ARM64
7 default " Allwinner Technology"
12 Select this dram controller driver for Sun4/5/7i platforms,
18 Select this dram controller driver for Sun6i platforms,
24 Select this dram controller driver for Sun8i platforms,
30 Select this dram controller driver for Sun8i platforms,
33 config DRAM_SUN8I_A83T
36 Select this dram controller driver for Sun8i platforms,
42 Select this dram controller driver for Sun9i platforms,
46 bool "Allwinner sun6i internal P2WI controller"
48 If you say yes to this option, support will be included for the
49 P2WI (Push/Pull 2 Wire Interface) controller embedded in some sunxi
51 The P2WI looks like an SMBus controller (which supports only byte
52 accesses), except that it only supports one slave device.
53 This interface is used to connect to specific PMIC devices (like the
59 Support for the PRCM (Power/Reset/Clock Management) unit available
63 bool "Sunxi AXP PMIC bus access helpers"
65 Select this PMIC bus access helpers for Sunxi platform PRCM or other
66 AXP family PMIC devices.
69 bool "Allwinner sunXi Reduced Serial Bus Driver"
71 Say y here to enable support for Allwinner's Reduced Serial Bus
72 (RSB) support. This controller is responsible for communicating
73 with various RSB based devices, such as AXP223, AXP8XX PMICs,
76 config SUNXI_HIGH_SRAM
80 Older Allwinner SoCs have their mask boot ROM mapped just below 4GB,
81 with the first SRAM region being located at address 0.
82 Some newer SoCs map the boot ROM at address 0 instead and move the
83 SRAM to 64KB, just behind the mask ROM.
84 Chips using the latter setup are supposed to select this option to
85 adjust the addresses accordingly.
87 # Note only one of these may be selected at a time! But hidden choices are
88 # not supported by Kconfig
89 config SUNXI_GEN_SUN4I
92 Select this for sunxi SoCs which have resets and clocks set up
93 as the original A10 (mach-sun4i).
95 config SUNXI_GEN_SUN6I
98 Select this for sunxi SoCs which have sun6i like periphery, like
99 separate ahb reset control registers, custom pmic bus, new style
105 Select this for sunxi SoCs which uses a DRAM controller like the
106 DesignWare controller used in H3, mainly SoCs after H3, which do
107 not have official open-source DRAM initialization code, but can
108 use modified H3 DRAM initialization code.
111 config SUNXI_DRAM_DW_16BIT
114 Select this for sunxi SoCs with DesignWare DRAM controller and
115 have only 16-bit memory buswidth.
117 config SUNXI_DRAM_DW_32BIT
120 Select this for sunxi SoCs with DesignWare DRAM controller with
121 32-bit memory buswidth.
124 config MACH_SUNXI_H3_H5
130 select SUNXI_DRAM_DW_32BIT
131 select SUNXI_GEN_SUN6I
135 prompt "Sunxi SoC Variant"
139 bool "sun4i (Allwinner A10)"
141 select ARM_CORTEX_CPU_IS_UP
144 select SUNXI_GEN_SUN4I
148 bool "sun5i (Allwinner A13)"
150 select ARM_CORTEX_CPU_IS_UP
153 select SUNXI_GEN_SUN4I
155 imply CONS_INDEX_2 if !DM_SERIAL
158 bool "sun6i (Allwinner A31)"
160 select CPU_V7_HAS_NONSEC
161 select CPU_V7_HAS_VIRT
162 select ARCH_SUPPORT_PSCI
167 select SUNXI_GEN_SUN6I
169 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
172 bool "sun7i (Allwinner A20)"
174 select CPU_V7_HAS_NONSEC
175 select CPU_V7_HAS_VIRT
176 select ARCH_SUPPORT_PSCI
179 select SUNXI_GEN_SUN4I
181 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
183 config MACH_SUN8I_A23
184 bool "sun8i (Allwinner A23)"
186 select CPU_V7_HAS_NONSEC
187 select CPU_V7_HAS_VIRT
188 select ARCH_SUPPORT_PSCI
189 select DRAM_SUN8I_A23
191 select SUNXI_GEN_SUN6I
193 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
194 imply CONS_INDEX_5 if !DM_SERIAL
196 config MACH_SUN8I_A33
197 bool "sun8i (Allwinner A33)"
199 select CPU_V7_HAS_NONSEC
200 select CPU_V7_HAS_VIRT
201 select ARCH_SUPPORT_PSCI
202 select DRAM_SUN8I_A33
204 select SUNXI_GEN_SUN6I
206 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
207 imply CONS_INDEX_5 if !DM_SERIAL
209 config MACH_SUN8I_A83T
210 bool "sun8i (Allwinner A83T)"
212 select DRAM_SUN8I_A83T
214 select SUNXI_GEN_SUN6I
215 select MMC_SUNXI_HAS_NEW_MODE
219 bool "sun8i (Allwinner H3)"
221 select CPU_V7_HAS_NONSEC
222 select CPU_V7_HAS_VIRT
223 select ARCH_SUPPORT_PSCI
224 select MACH_SUNXI_H3_H5
225 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
227 config MACH_SUN8I_R40
228 bool "sun8i (Allwinner R40)"
230 select CPU_V7_HAS_NONSEC
231 select CPU_V7_HAS_VIRT
232 select ARCH_SUPPORT_PSCI
233 select SUNXI_GEN_SUN6I
236 select SUNXI_DRAM_DW_32BIT
238 config MACH_SUN8I_V3S
239 bool "sun8i (Allwinner V3s)"
241 select CPU_V7_HAS_NONSEC
242 select CPU_V7_HAS_VIRT
243 select ARCH_SUPPORT_PSCI
244 select SUNXI_GEN_SUN6I
246 select SUNXI_DRAM_DW_16BIT
248 select ARMV7_BOOT_SEC_DEFAULT if OLD_SUNXI_KERNEL_COMPAT
251 bool "sun9i (Allwinner A80)"
255 select SUNXI_HIGH_SRAM
256 select SUNXI_GEN_SUN6I
261 bool "sun50i (Allwinner A64)"
266 select SUNXI_GEN_SUN6I
267 select SUNXI_HIGH_SRAM
270 select SUNXI_DRAM_DW_32BIT
274 config MACH_SUN50I_H5
275 bool "sun50i (Allwinner H5)"
277 select MACH_SUNXI_H3_H5
278 select SUNXI_HIGH_SRAM
284 # The sun8i SoCs share a lot, this helps to avoid a lot of "if A23 || A33"
289 default y if MACH_SUN8I_A23
290 default y if MACH_SUN8I_A33
291 default y if MACH_SUN8I_A83T
292 default y if MACH_SUNXI_H3_H5
293 default y if MACH_SUN8I_R40
294 default y if MACH_SUN8I_V3S
296 config RESERVE_ALLWINNER_BOOT0_HEADER
297 bool "reserve space for Allwinner boot0 header"
298 select ENABLE_ARM_SOC_BOOT0_HOOK
300 Prepend a 1536 byte (empty) header to the U-Boot image file, to be
301 filled with magic values post build. The Allwinner provided boot0
302 blob relies on this information to load and execute U-Boot.
303 Only needed on 64-bit Allwinner boards so far when using boot0.
305 config ARM_BOOT_HOOK_RMR
309 select ENABLE_ARM_SOC_BOOT0_HOOK
311 Insert some ARM32 code at the very beginning of the U-Boot binary
312 which uses an RMR register write to bring the core into AArch64 mode.
313 The very first instruction acts as a switch, since it's carefully
314 chosen to be a NOP in one mode and a branch in the other, so the
315 code would only be executed if not already in AArch64.
316 This allows both the SPL and the U-Boot proper to be entered in
317 either mode and switch to AArch64 if needed.
320 config SUNXI_DRAM_DDR3
323 config SUNXI_DRAM_DDR2
326 config SUNXI_DRAM_LPDDR3
330 prompt "DRAM Type and Timing"
331 default SUNXI_DRAM_DDR3_1333 if !MACH_SUN8I_V3S
332 default SUNXI_DRAM_DDR2_V3S if MACH_SUN8I_V3S
334 config SUNXI_DRAM_DDR3_1333
336 select SUNXI_DRAM_DDR3
337 depends on !MACH_SUN8I_V3S
339 This option is the original only supported memory type, which suits
340 many H3/H5/A64 boards available now.
342 config SUNXI_DRAM_LPDDR3_STOCK
343 bool "LPDDR3 with Allwinner stock configuration"
344 select SUNXI_DRAM_LPDDR3
346 This option is the LPDDR3 timing used by the stock boot0 by
349 config SUNXI_DRAM_DDR2_V3S
350 bool "DDR2 found in V3s chip"
351 select SUNXI_DRAM_DDR2
352 depends on MACH_SUN8I_V3S
354 This option is only for the DDR2 memory chip which is co-packaged in
361 int "sunxi dram type"
362 depends on MACH_SUN8I_A83T
365 Set the dram type, 3: DDR3, 7: LPDDR3
368 int "sunxi dram clock speed"
369 default 792 if MACH_SUN9I
370 default 648 if MACH_SUN8I_R40
371 default 312 if MACH_SUN6I || MACH_SUN8I
372 default 360 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || \
374 default 672 if MACH_SUN50I
376 Set the dram clock speed, valid range 240 - 480 (prior to sun9i),
377 must be a multiple of 24. For the sun9i (A80), the tested values
378 (for DDR3-1600) are 312 to 792.
380 if MACH_SUN5I || MACH_SUN7I
382 int "sunxi mbus clock speed"
385 Set the mbus clock speed. The maximum on sun5i hardware is 300MHz.
390 int "sunxi dram zq value"
391 default 123 if MACH_SUN4I || MACH_SUN5I || MACH_SUN6I || MACH_SUN8I
392 default 127 if MACH_SUN7I
393 default 14779 if MACH_SUN8I_V3S
394 default 3881979 if MACH_SUN8I_R40
395 default 4145117 if MACH_SUN9I
396 default 3881915 if MACH_SUN50I
398 Set the dram zq value.
401 bool "sunxi dram odt enable"
402 default n if !MACH_SUN8I_A23
403 default y if MACH_SUN8I_A23
404 default y if MACH_SUN8I_R40
405 default y if MACH_SUN50I
407 Select this to enable dram odt (on die termination).
409 if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
411 int "sunxi dram emr1 value"
412 default 0 if MACH_SUN4I
413 default 4 if MACH_SUN5I || MACH_SUN7I
415 Set the dram controller emr1 value.
418 hex "sunxi dram tpr3 value"
421 Set the dram controller tpr3 parameter. This parameter configures
422 the delay on the command lane and also phase shifts, which are
423 applied for sampling incoming read data. The default value 0
424 means that no phase/delay adjustments are necessary. Properly
425 configuring this parameter increases reliability at high DRAM
428 config DRAM_DQS_GATING_DELAY
429 hex "sunxi dram dqs_gating_delay value"
432 Set the dram controller dqs_gating_delay parmeter. Each byte
433 encodes the DQS gating delay for each byte lane. The delay
434 granularity is 1/4 cycle. For example, the value 0x05060606
435 means that the delay is 5 quarter-cycles for one lane (1.25
436 cycles) and 6 quarter-cycles (1.5 cycles) for 3 other lanes.
437 The default value 0 means autodetection. The results of hardware
438 autodetection are not very reliable and depend on the chip
439 temperature (sometimes producing different results on cold start
440 and warm reboot). But the accuracy of hardware autodetection
441 is usually good enough, unless running at really high DRAM
442 clocks speeds (up to 600MHz). If unsure, keep as 0.
445 prompt "sunxi dram timings"
446 default DRAM_TIMINGS_VENDOR_MAGIC
448 Select the timings of the DDR3 chips.
450 config DRAM_TIMINGS_VENDOR_MAGIC
451 bool "Magic vendor timings from Android"
453 The same DRAM timings as in the Allwinner boot0 bootloader.
455 config DRAM_TIMINGS_DDR3_1066F_1333H
456 bool "JEDEC DDR3-1333H with down binning to DDR3-1066F"
458 Use the timings of the standard JEDEC DDR3-1066F speed bin for
459 DRAM_CLK <= 533MHz and the timings of the DDR3-1333H speed bin
460 for DRAM_CLK > 533MHz. This covers the majority of DDR3 chips
461 used in Allwinner A10/A13/A20 devices. In the case of DDR3-1333
462 or DDR3-1600 chips, be sure to check the DRAM datasheet to confirm
463 that down binning to DDR3-1066F is supported (because DDR3-1066F
464 uses a bit faster timings than DDR3-1333H).
466 config DRAM_TIMINGS_DDR3_800E_1066G_1333J
467 bool "JEDEC DDR3-800E / DDR3-1066G / DDR3-1333J"
469 Use the timings of the slowest possible JEDEC speed bin for the
470 selected DRAM_CLK. Depending on the DRAM_CLK value, it may be
471 DDR3-800E, DDR3-1066G or DDR3-1333J.
478 config DRAM_ODT_CORRECTION
479 int "sunxi dram odt correction value"
482 Set the dram odt correction value (range -255 - 255). In allwinner
483 fex files, this option is found in bits 8-15 of the u32 odt_en variable
484 in the [dram] section. When bit 31 of the odt_en variable is set
485 then the correction is negative. Usually the value for this is 0.
489 default 1008000000 if MACH_SUN4I
490 default 1008000000 if MACH_SUN5I
491 default 1008000000 if MACH_SUN6I
492 default 912000000 if MACH_SUN7I
493 default 816000000 if MACH_SUN50I || MACH_SUN50I_H5
494 default 1008000000 if MACH_SUN8I
495 default 1008000000 if MACH_SUN9I
497 config SYS_CONFIG_NAME
498 default "sun4i" if MACH_SUN4I
499 default "sun5i" if MACH_SUN5I
500 default "sun6i" if MACH_SUN6I
501 default "sun7i" if MACH_SUN7I
502 default "sun8i" if MACH_SUN8I
503 default "sun9i" if MACH_SUN9I
504 default "sun50i" if MACH_SUN50I
513 bool "UART0 on MicroSD breakout board"
516 Repurpose the SD card slot for getting access to the UART0 serial
517 console. Primarily useful only for low level u-boot debugging on
518 tablets, where normal UART0 is difficult to access and requires
519 device disassembly and/or soldering. As the SD card can't be used
520 at the same time, the system can be only booted in the FEL mode.
521 Only enable this if you really know what you are doing.
523 config OLD_SUNXI_KERNEL_COMPAT
524 bool "Enable workarounds for booting old kernels"
527 Set this to enable various workarounds for old kernels, this results in
528 sub-optimal settings for newer kernels, only enable if needed.
531 string "MAC power pin"
534 Set the pin used to power the MAC. This takes a string in the format
535 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
538 string "Card detect pin for mmc0"
539 default "PF6" if MACH_SUN8I_A83T || MACH_SUNXI_H3_H5 || MACH_SUN50I
542 Set the card detect pin for mmc0, leave empty to not use cd. This
543 takes a string in the format understood by sunxi_name_to_gpio, e.g.
544 PH1 for pin 1 of port H.
547 string "Card detect pin for mmc1"
550 See MMC0_CD_PIN help text.
553 string "Card detect pin for mmc2"
556 See MMC0_CD_PIN help text.
559 string "Card detect pin for mmc3"
562 See MMC0_CD_PIN help text.
565 string "Pins for mmc1"
568 Set the pins used for mmc1, when applicable. This takes a string in the
569 format understood by sunxi_name_to_gpio_bank, e.g. PH for port H.
572 string "Pins for mmc2"
575 See MMC1_PINS help text.
578 string "Pins for mmc3"
581 See MMC1_PINS help text.
583 config MMC_SUNXI_SLOT_EXTRA
584 int "mmc extra slot number"
587 sunxi builds always enable mmc0, some boards also have a second sdcard
588 slot or emmc on mmc1 - mmc3. Setting this to 1, 2 or 3 will enable
591 config INITIAL_USB_SCAN_DELAY
592 int "delay initial usb scan by x ms to allow builtin devices to init"
595 Some boards have on board usb devices which need longer than the
596 USB spec's 1 second to connect from board powerup. Set this config
597 option to a non 0 value to add an extra delay before the first usb
601 string "Vbus enable pin for usb0 (otg)"
604 Set the Vbus enable pin for usb0 (otg). This takes a string in the
605 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
608 string "Vbus detect pin for usb0 (otg)"
611 Set the Vbus detect pin for usb0 (otg). This takes a string in the
612 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
615 string "ID detect pin for usb0 (otg)"
618 Set the ID detect pin for usb0 (otg). This takes a string in the
619 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
622 string "Vbus enable pin for usb1 (ehci0)"
623 default "PH6" if MACH_SUN4I || MACH_SUN7I
624 default "PH27" if MACH_SUN6I
626 Set the Vbus enable pin for usb1 (ehci0, usb0 is the otg). This takes
627 a string in the format understood by sunxi_name_to_gpio, e.g.
628 PH1 for pin 1 of port H.
631 string "Vbus enable pin for usb2 (ehci1)"
632 default "PH3" if MACH_SUN4I || MACH_SUN7I
633 default "PH24" if MACH_SUN6I
635 See USB1_VBUS_PIN help text.
638 string "Vbus enable pin for usb3 (ehci2)"
641 See USB1_VBUS_PIN help text.
644 bool "Enable I2C/TWI controller 0"
645 default y if MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I_R40
646 default n if MACH_SUN6I || MACH_SUN8I
649 This allows enabling I2C/TWI controller 0 by muxing its pins, enabling
650 its clock and setting up the bus. This is especially useful on devices
651 with slaves connected to the bus or with pins exposed through e.g. an
652 expansion port/header.
655 bool "Enable I2C/TWI controller 1"
659 See I2C0_ENABLE help text.
662 bool "Enable I2C/TWI controller 2"
666 See I2C0_ENABLE help text.
668 if MACH_SUN6I || MACH_SUN7I
670 bool "Enable I2C/TWI controller 3"
674 See I2C0_ENABLE help text.
679 bool "Enable the PRCM I2C/TWI controller"
680 # This is used for the pmic on H3
681 default y if SY8106A_POWER
684 Set this to y to enable the I2C controller which is part of the PRCM.
689 bool "Enable I2C/TWI controller 4"
693 See I2C0_ENABLE help text.
697 bool "Enable support for gpio-s on axp PMICs"
700 Say Y here to enable support for the gpio pins of the axp PMIC ICs.
703 bool "Enable graphical uboot console on HDMI, LCD or VGA"
704 depends on !MACH_SUN8I_A83T
705 depends on !MACH_SUNXI_H3_H5
706 depends on !MACH_SUN8I_R40
707 depends on !MACH_SUN8I_V3S
708 depends on !MACH_SUN9I
709 depends on !MACH_SUN50I
711 imply VIDEO_DT_SIMPLEFB
714 Say Y here to add support for using a cfb console on the HDMI, LCD
715 or VGA output found on most sunxi devices. See doc/README.video for
716 info on how to select the video output and mode.
719 bool "HDMI output support"
720 depends on VIDEO_SUNXI && !MACH_SUN8I
723 Say Y here to add support for outputting video over HDMI.
726 bool "VGA output support"
727 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN7I)
730 Say Y here to add support for outputting video over VGA.
732 config VIDEO_VGA_VIA_LCD
733 bool "VGA via LCD controller support"
734 depends on VIDEO_SUNXI && (MACH_SUN5I || MACH_SUN6I || MACH_SUN8I)
737 Say Y here to add support for external DACs connected to the parallel
738 LCD interface driving a VGA connector, such as found on the
741 config VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH
742 bool "Force sync active high for VGA via LCD controller support"
743 depends on VIDEO_VGA_VIA_LCD
746 Say Y here if you've a board which uses opendrain drivers for the vga
747 hsync and vsync signals. Opendrain drivers cannot generate steep enough
748 positive edges for a stable video output, so on boards with opendrain
749 drivers the sync signals must always be active high.
751 config VIDEO_VGA_EXTERNAL_DAC_EN
752 string "LCD panel power enable pin"
753 depends on VIDEO_VGA_VIA_LCD
756 Set the enable pin for the external VGA DAC. This takes a string in the
757 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
759 config VIDEO_COMPOSITE
760 bool "Composite video output support"
761 depends on VIDEO_SUNXI && (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
764 Say Y here to add support for outputting composite video.
766 config VIDEO_LCD_MODE
767 string "LCD panel timing details"
768 depends on VIDEO_SUNXI
771 LCD panel timing details string, leave empty if there is no LCD panel.
772 This is in drivers/video/videomodes.c: video_get_params() format, e.g.
773 x:800,y:480,depth:18,pclk_khz:33000,le:16,ri:209,up:22,lo:22,hs:30,vs:1,sync:0,vmode:0
774 Also see: http://linux-sunxi.org/LCD
776 config VIDEO_LCD_DCLK_PHASE
777 int "LCD panel display clock phase"
778 depends on VIDEO_SUNXI || DM_VIDEO
781 Select LCD panel display clock phase shift, range 0-3.
783 config VIDEO_LCD_POWER
784 string "LCD panel power enable pin"
785 depends on VIDEO_SUNXI
788 Set the power enable pin for the LCD panel. This takes a string in the
789 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
791 config VIDEO_LCD_RESET
792 string "LCD panel reset pin"
793 depends on VIDEO_SUNXI
796 Set the reset pin for the LCD panel. This takes a string in the format
797 understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
799 config VIDEO_LCD_BL_EN
800 string "LCD panel backlight enable pin"
801 depends on VIDEO_SUNXI
804 Set the backlight enable pin for the LCD panel. This takes a string in the
805 the format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
808 config VIDEO_LCD_BL_PWM
809 string "LCD panel backlight pwm pin"
810 depends on VIDEO_SUNXI
813 Set the backlight pwm pin for the LCD panel. This takes a string in the
814 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
816 config VIDEO_LCD_BL_PWM_ACTIVE_LOW
817 bool "LCD panel backlight pwm is inverted"
818 depends on VIDEO_SUNXI
821 Set this if the backlight pwm output is active low.
823 config VIDEO_LCD_PANEL_I2C
824 bool "LCD panel needs to be configured via i2c"
825 depends on VIDEO_SUNXI
829 Say y here if the LCD panel needs to be configured via i2c. This
830 will add a bitbang i2c controller using gpios to talk to the LCD.
832 config VIDEO_LCD_PANEL_I2C_SDA
833 string "LCD panel i2c interface SDA pin"
834 depends on VIDEO_LCD_PANEL_I2C
837 Set the SDA pin for the LCD i2c interface. This takes a string in the
838 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
840 config VIDEO_LCD_PANEL_I2C_SCL
841 string "LCD panel i2c interface SCL pin"
842 depends on VIDEO_LCD_PANEL_I2C
845 Set the SCL pin for the LCD i2c interface. This takes a string in the
846 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of port H.
849 # Note only one of these may be selected at a time! But hidden choices are
850 # not supported by Kconfig
851 config VIDEO_LCD_IF_PARALLEL
854 config VIDEO_LCD_IF_LVDS
862 bool "Display Engine 2 video driver"
866 imply VIDEO_DT_SIMPLEFB
869 Say y here if you want to build DE2 video driver which is present on
870 newer SoCs. Currently only HDMI output is supported.
874 prompt "LCD panel support"
875 depends on VIDEO_SUNXI
877 Select which type of LCD panel to support.
879 config VIDEO_LCD_PANEL_PARALLEL
880 bool "Generic parallel interface LCD panel"
881 select VIDEO_LCD_IF_PARALLEL
883 config VIDEO_LCD_PANEL_LVDS
884 bool "Generic lvds interface LCD panel"
885 select VIDEO_LCD_IF_LVDS
887 config VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828
888 bool "MIPI 4-lane, 513Mbps LCD panel via SSD2828 bridge chip"
889 select VIDEO_LCD_SSD2828
890 select VIDEO_LCD_IF_PARALLEL
892 7.85" 768x1024 LCD panels, such as LG LP079X01 or AUO B079XAN01.0
894 config VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804
895 bool "eDP 4-lane, 1.62G LCD panel via ANX9804 bridge chip"
896 select VIDEO_LCD_ANX9804
897 select VIDEO_LCD_IF_PARALLEL
898 select VIDEO_LCD_PANEL_I2C
900 Select this for eDP LCD panels with 4 lanes running at 1.62G,
901 connected via an ANX9804 bridge chip.
903 config VIDEO_LCD_PANEL_HITACHI_TX18D42VM
904 bool "Hitachi tx18d42vm LCD panel"
905 select VIDEO_LCD_HITACHI_TX18D42VM
906 select VIDEO_LCD_IF_LVDS
908 7.85" 1024x768 Hitachi tx18d42vm LCD panel support
910 config VIDEO_LCD_TL059WV5C0
911 bool "tl059wv5c0 LCD panel"
912 select VIDEO_LCD_PANEL_I2C
913 select VIDEO_LCD_IF_PARALLEL
915 6" 480x800 tl059wv5c0 panel support, as used on the Utoo P66 and
916 Aigo M60/M608/M606 tablets.
921 string "SATA power pin"
924 Set the pins used to power the SATA. This takes a string in the
925 format understood by sunxi_name_to_gpio, e.g. PH1 for pin 1 of
929 int "GMAC Transmit Clock Delay Chain"
932 Set the GMAC Transmit Clock Delay Chain value.
934 config SPL_STACK_R_ADDR
935 default 0x4fe00000 if MACH_SUN4I
936 default 0x4fe00000 if MACH_SUN5I
937 default 0x4fe00000 if MACH_SUN6I
938 default 0x4fe00000 if MACH_SUN7I
939 default 0x4fe00000 if MACH_SUN8I
940 default 0x2fe00000 if MACH_SUN9I
941 default 0x4fe00000 if MACH_SUN50I
944 bool "Support for SPI Flash on Allwinner SoCs in SPL"
945 depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUNXI_H3_H5 || MACH_SUN50I
947 Enable support for SPI Flash. This option allows SPL to read from
948 sunxi SPI Flash. It uses the same method as the boot ROM, so does
949 not need any extra configuration.