1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
12 #include <asm/secure.h>
14 #define BOOT_API_A7_CORE0_MAGIC_NUMBER 0xCA7FACE0
15 #define BOOT_API_A7_CORE1_MAGIC_NUMBER 0xCA7FACE1
17 #define MPIDR_AFF0 GENMASK(7, 0)
19 #define RCC_MP_GRSTCSETR (STM32_RCC_BASE + 0x0404)
20 #define RCC_MP_GRSTCSETR_MPUP1RST BIT(5)
21 #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
22 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
24 #define STM32MP1_PSCI_NR_CPUS 2
25 #if STM32MP1_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS
26 #error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS"
29 u8 psci_state[STM32MP1_PSCI_NR_CPUS] __secure_data = {
30 PSCI_AFFINITY_LEVEL_ON,
31 PSCI_AFFINITY_LEVEL_OFF};
33 static u32 __secure_data cntfrq;
35 static u32 __secure cp15_read_cntfrq(void)
39 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq));
44 static void __secure cp15_write_cntfrq(u32 frq)
46 asm volatile ("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq));
49 static inline void psci_set_state(int cpu, u8 state)
51 psci_state[cpu] = state;
56 static u32 __secure stm32mp_get_gicd_base_address(void)
60 /* get the GIC base address from the CBAR register */
61 asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
63 return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
66 static void __secure stm32mp_raise_sgi0(int cpu)
70 gic_dist_addr = stm32mp_get_gicd_base_address();
72 /* ask cpu with SGI0 */
73 writel((BIT(cpu) << 16), gic_dist_addr + GICD_SGIR);
76 void __secure psci_arch_cpu_entry(void)
78 u32 cpu = psci_get_cpu_id();
80 psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
82 /* write the saved cntfrq */
83 cp15_write_cntfrq(cntfrq);
85 /* reset magic in TAMP register */
86 writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
89 s32 __secure psci_features(u32 function_id, u32 psci_fid)
92 case ARM_PSCI_0_2_FN_PSCI_VERSION:
93 case ARM_PSCI_0_2_FN_CPU_OFF:
94 case ARM_PSCI_0_2_FN_CPU_ON:
95 case ARM_PSCI_0_2_FN_AFFINITY_INFO:
96 case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
97 case ARM_PSCI_0_2_FN_SYSTEM_OFF:
98 case ARM_PSCI_0_2_FN_SYSTEM_RESET:
101 return ARM_PSCI_RET_NI;
104 u32 __secure psci_version(void)
106 return ARM_PSCI_VER_1_0;
109 s32 __secure psci_affinity_info(u32 function_id, u32 target_affinity,
110 u32 lowest_affinity_level)
112 u32 cpu = target_affinity & MPIDR_AFF0;
114 if (lowest_affinity_level > 0)
115 return ARM_PSCI_RET_INVAL;
117 if (target_affinity & ~MPIDR_AFF0)
118 return ARM_PSCI_RET_INVAL;
120 if (cpu >= STM32MP1_PSCI_NR_CPUS)
121 return ARM_PSCI_RET_INVAL;
123 return psci_state[cpu];
126 u32 __secure psci_migrate_info_type(void)
129 * in Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
130 * return 2 = Trusted OS is either not present or does not require
131 * migration, system of this type does not require the caller
132 * to use the MIGRATE function.
133 * MIGRATE function calls return NOT_SUPPORTED.
138 s32 __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
141 u32 cpu = target_cpu & MPIDR_AFF0;
143 if (target_cpu & ~MPIDR_AFF0)
144 return ARM_PSCI_RET_INVAL;
146 if (cpu >= STM32MP1_PSCI_NR_CPUS)
147 return ARM_PSCI_RET_INVAL;
149 if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
150 return ARM_PSCI_RET_ALREADY_ON;
152 /* read and save cntfrq of current cpu to write on target cpu */
153 cntfrq = cp15_read_cntfrq();
155 /* reset magic in TAMP register */
156 if (readl(TAMP_BACKUP_MAGIC_NUMBER))
157 writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
159 * ROM code need a first SGI0 after core reset
160 * core is ready when magic is set to 0 in ROM code
162 while (readl(TAMP_BACKUP_MAGIC_NUMBER))
163 stm32mp_raise_sgi0(cpu);
165 /* store target PC and context id*/
166 psci_save(cpu, pc, context_id);
168 /* write entrypoint in backup RAM register */
169 writel((u32)&psci_cpu_entry, TAMP_BACKUP_BRANCH_ADDRESS);
170 psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING);
172 /* write magic number in backup register */
174 writel(BOOT_API_A7_CORE1_MAGIC_NUMBER,
175 TAMP_BACKUP_MAGIC_NUMBER);
177 writel(BOOT_API_A7_CORE0_MAGIC_NUMBER,
178 TAMP_BACKUP_MAGIC_NUMBER);
180 /* Generate an IT to start the core */
181 stm32mp_raise_sgi0(cpu);
183 return ARM_PSCI_RET_SUCCESS;
186 s32 __secure psci_cpu_off(void)
190 cpu = psci_get_cpu_id();
192 psci_cpu_off_common();
193 psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF);
195 /* reset core: wfi is managed by BootRom */
197 writel(RCC_MP_GRSTCSETR_MPUP1RST, RCC_MP_GRSTCSETR);
199 writel(RCC_MP_GRSTCSETR_MPUP0RST, RCC_MP_GRSTCSETR);
201 /* just waiting reset */
206 void __secure psci_system_reset(void)
209 writel(RCC_MP_GRSTCSETR_MPSYSRST, RCC_MP_GRSTCSETR);
210 /* just waiting reset */
215 void __secure psci_system_off(void)
217 /* System Off is not managed, waiting user power off
218 * TODO: handle I2C write in PMIC Main Control register bit 0 = SWOFF