1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
13 #include <asm/secure.h>
15 #define BOOT_API_A7_CORE0_MAGIC_NUMBER 0xCA7FACE0
16 #define BOOT_API_A7_CORE1_MAGIC_NUMBER 0xCA7FACE1
18 #define MPIDR_AFF0 GENMASK(7, 0)
20 #define RCC_MP_GRSTCSETR (STM32_RCC_BASE + 0x0404)
21 #define RCC_MP_GRSTCSETR_MPUP1RST BIT(5)
22 #define RCC_MP_GRSTCSETR_MPUP0RST BIT(4)
23 #define RCC_MP_GRSTCSETR_MPSYSRST BIT(0)
25 #define STM32MP1_PSCI_NR_CPUS 2
26 #if STM32MP1_PSCI_NR_CPUS > CONFIG_ARMV7_PSCI_NR_CPUS
27 #error "invalid value for CONFIG_ARMV7_PSCI_NR_CPUS"
30 u8 psci_state[STM32MP1_PSCI_NR_CPUS] __secure_data = {
31 PSCI_AFFINITY_LEVEL_ON,
32 PSCI_AFFINITY_LEVEL_OFF};
34 static u32 __secure_data cntfrq;
36 static u32 __secure cp15_read_cntfrq(void)
40 asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (frq));
45 static void __secure cp15_write_cntfrq(u32 frq)
47 asm volatile ("mcr p15, 0, %0, c14, c0, 0" : : "r" (frq));
50 static inline void psci_set_state(int cpu, u8 state)
52 psci_state[cpu] = state;
57 static u32 __secure stm32mp_get_gicd_base_address(void)
61 /* get the GIC base address from the CBAR register */
62 asm("mrc p15, 4, %0, c15, c0, 0\n" : "=r" (periphbase));
64 return (periphbase & CBAR_MASK) + GIC_DIST_OFFSET;
67 static void __secure stm32mp_raise_sgi0(int cpu)
71 gic_dist_addr = stm32mp_get_gicd_base_address();
73 /* ask cpu with SGI0 */
74 writel((BIT(cpu) << 16), gic_dist_addr + GICD_SGIR);
77 void __secure psci_arch_cpu_entry(void)
79 u32 cpu = psci_get_cpu_id();
81 psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON);
83 /* write the saved cntfrq */
84 cp15_write_cntfrq(cntfrq);
86 /* reset magic in TAMP register */
87 writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
90 s32 __secure psci_features(u32 function_id, u32 psci_fid)
93 case ARM_PSCI_0_2_FN_PSCI_VERSION:
94 case ARM_PSCI_0_2_FN_CPU_OFF:
95 case ARM_PSCI_0_2_FN_CPU_ON:
96 case ARM_PSCI_0_2_FN_AFFINITY_INFO:
97 case ARM_PSCI_0_2_FN_MIGRATE_INFO_TYPE:
98 case ARM_PSCI_0_2_FN_SYSTEM_OFF:
99 case ARM_PSCI_0_2_FN_SYSTEM_RESET:
102 return ARM_PSCI_RET_NI;
105 u32 __secure psci_version(void)
107 return ARM_PSCI_VER_1_0;
110 s32 __secure psci_affinity_info(u32 function_id, u32 target_affinity,
111 u32 lowest_affinity_level)
113 u32 cpu = target_affinity & MPIDR_AFF0;
115 if (lowest_affinity_level > 0)
116 return ARM_PSCI_RET_INVAL;
118 if (target_affinity & ~MPIDR_AFF0)
119 return ARM_PSCI_RET_INVAL;
121 if (cpu >= STM32MP1_PSCI_NR_CPUS)
122 return ARM_PSCI_RET_INVAL;
124 return psci_state[cpu];
127 u32 __secure psci_migrate_info_type(void)
130 * in Power_State_Coordination_Interface_PDD_v1_1_DEN0022D.pdf
131 * return 2 = Trusted OS is either not present or does not require
132 * migration, system of this type does not require the caller
133 * to use the MIGRATE function.
134 * MIGRATE function calls return NOT_SUPPORTED.
139 s32 __secure psci_cpu_on(u32 function_id, u32 target_cpu, u32 pc,
142 u32 cpu = target_cpu & MPIDR_AFF0;
144 if (target_cpu & ~MPIDR_AFF0)
145 return ARM_PSCI_RET_INVAL;
147 if (cpu >= STM32MP1_PSCI_NR_CPUS)
148 return ARM_PSCI_RET_INVAL;
150 if (psci_state[cpu] == PSCI_AFFINITY_LEVEL_ON)
151 return ARM_PSCI_RET_ALREADY_ON;
153 /* read and save cntfrq of current cpu to write on target cpu */
154 cntfrq = cp15_read_cntfrq();
156 /* reset magic in TAMP register */
157 if (readl(TAMP_BACKUP_MAGIC_NUMBER))
158 writel(0xFFFFFFFF, TAMP_BACKUP_MAGIC_NUMBER);
160 * ROM code need a first SGI0 after core reset
161 * core is ready when magic is set to 0 in ROM code
163 while (readl(TAMP_BACKUP_MAGIC_NUMBER))
164 stm32mp_raise_sgi0(cpu);
166 /* store target PC and context id*/
167 psci_save(cpu, pc, context_id);
169 /* write entrypoint in backup RAM register */
170 writel((u32)&psci_cpu_entry, TAMP_BACKUP_BRANCH_ADDRESS);
171 psci_set_state(cpu, PSCI_AFFINITY_LEVEL_ON_PENDING);
173 /* write magic number in backup register */
175 writel(BOOT_API_A7_CORE1_MAGIC_NUMBER,
176 TAMP_BACKUP_MAGIC_NUMBER);
178 writel(BOOT_API_A7_CORE0_MAGIC_NUMBER,
179 TAMP_BACKUP_MAGIC_NUMBER);
181 /* Generate an IT to start the core */
182 stm32mp_raise_sgi0(cpu);
184 return ARM_PSCI_RET_SUCCESS;
187 s32 __secure psci_cpu_off(void)
191 cpu = psci_get_cpu_id();
193 psci_cpu_off_common();
194 psci_set_state(cpu, PSCI_AFFINITY_LEVEL_OFF);
196 /* reset core: wfi is managed by BootRom */
198 writel(RCC_MP_GRSTCSETR_MPUP1RST, RCC_MP_GRSTCSETR);
200 writel(RCC_MP_GRSTCSETR_MPUP0RST, RCC_MP_GRSTCSETR);
202 /* just waiting reset */
207 void __secure psci_system_reset(void)
210 writel(RCC_MP_GRSTCSETR_MPSYSRST, RCC_MP_GRSTCSETR);
211 /* just waiting reset */
216 void __secure psci_system_off(void)
218 /* System Off is not managed, waiting user power off
219 * TODO: handle I2C write in PMIC Main Control register bit 0 = SWOFF