1 /* SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
10 * Peripheral memory map
11 * only address used before device tree parsing
13 #define STM32_RCC_BASE 0x50000000
14 #define STM32_PWR_BASE 0x50001000
15 #define STM32_DBGMCU_BASE 0x50081000
16 #define STM32_TZC_BASE 0x5C006000
17 #define STM32_ETZPC_BASE 0x5C007000
18 #define STM32_TAMP_BASE 0x5C00A000
20 #define STM32_USART1_BASE 0x5C000000
21 #define STM32_USART2_BASE 0x4000E000
22 #define STM32_USART3_BASE 0x4000F000
23 #define STM32_UART4_BASE 0x40010000
24 #define STM32_UART5_BASE 0x40011000
25 #define STM32_USART6_BASE 0x44003000
26 #define STM32_UART7_BASE 0x40018000
27 #define STM32_UART8_BASE 0x40019000
29 #define STM32_SYSRAM_BASE 0x2FFC0000
30 #define STM32_SYSRAM_SIZE SZ_256K
32 #define STM32_DDR_BASE 0xC0000000
33 #define STM32_DDR_SIZE SZ_1G
36 /* enumerated used to identify the SYSCON driver instance */
38 STM32MP_SYSCON_UNKNOWN,
42 STM32MP_SYSCON_SYSCFG,
46 * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT
47 * - boot device = bit 8:4
48 * - boot instance = bit 3:0
50 #define BOOT_TYPE_MASK 0xF0
51 #define BOOT_TYPE_SHIFT 4
52 #define BOOT_INSTANCE_MASK 0x0F
53 #define BOOT_INSTANCE_SHIFT 0
57 BOOT_FLASH_SD_1 = 0x11,
58 BOOT_FLASH_SD_2 = 0x12,
59 BOOT_FLASH_SD_3 = 0x13,
61 BOOT_FLASH_EMMC = 0x20,
62 BOOT_FLASH_EMMC_1 = 0x21,
63 BOOT_FLASH_EMMC_2 = 0x22,
64 BOOT_FLASH_EMMC_3 = 0x23,
66 BOOT_FLASH_NAND = 0x30,
67 BOOT_FLASH_NAND_FMC = 0x31,
69 BOOT_FLASH_NOR = 0x40,
70 BOOT_FLASH_NOR_QSPI = 0x41,
72 BOOT_SERIAL_UART = 0x50,
73 BOOT_SERIAL_UART_1 = 0x51,
74 BOOT_SERIAL_UART_2 = 0x52,
75 BOOT_SERIAL_UART_3 = 0x53,
76 BOOT_SERIAL_UART_4 = 0x54,
77 BOOT_SERIAL_UART_5 = 0x55,
78 BOOT_SERIAL_UART_6 = 0x56,
79 BOOT_SERIAL_UART_7 = 0x57,
80 BOOT_SERIAL_UART_8 = 0x58,
82 BOOT_SERIAL_USB = 0x60,
83 BOOT_SERIAL_USB_OTG = 0x62,
87 #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x)
88 #define TAMP_BACKUP_MAGIC_NUMBER TAMP_BACKUP_REGISTER(4)
89 #define TAMP_BACKUP_BRANCH_ADDRESS TAMP_BACKUP_REGISTER(5)
90 #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(20)
91 #define TAMP_BOOTCOUNT TAMP_BACKUP_REGISTER(21)
93 #define TAMP_BOOT_MODE_MASK GENMASK(15, 8)
94 #define TAMP_BOOT_MODE_SHIFT 8
95 #define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4)
96 #define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0)
97 #define TAMP_BOOT_FORCED_MASK GENMASK(7, 0)
99 enum forced_boot_mode {
101 BOOT_FASTBOOT = 0x01,
102 BOOT_RECOVERY = 0x02,
103 BOOT_STM32PROG = 0x03,
104 BOOT_UMS_MMC0 = 0x10,
105 BOOT_UMS_MMC1 = 0x11,
106 BOOT_UMS_MMC2 = 0x12,
109 /* offset used for BSEC driver: misc_read and misc_write */
110 #define STM32_BSEC_SHADOW_OFFSET 0x0
111 #define STM32_BSEC_SHADOW(id) (STM32_BSEC_SHADOW_OFFSET + (id) * 4)
112 #define STM32_BSEC_OTP_OFFSET 0x80000000
113 #define STM32_BSEC_OTP(id) (STM32_BSEC_OTP_OFFSET + (id) * 4)
115 #define BSEC_OTP_BOARD 59
117 #endif /* __ASSEMBLY__*/
118 #endif /* _MACH_STM32_H_ */