2 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
4 * SPDX-License-Identifier: GPL-2.0+ BSD-3-Clause
9 #include <asm/arch/stm32.h>
12 #define RCC_TZCR (STM32_RCC_BASE + 0x00)
13 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
14 #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
15 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
16 #define RCC_BDCR_VSWRST BIT(31)
17 #define RCC_BDCR_RTCSRC GENMASK(17, 16)
18 #define RCC_DBGCFGR_DBGCKEN BIT(8)
20 /* Security register */
21 #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
22 #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
24 #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
25 #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
26 #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
28 #define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
30 #define PWR_CR1 (STM32_PWR_BASE + 0x00)
31 #define PWR_CR1_DBP BIT(8)
34 #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
35 #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
37 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
38 static void security_init(void)
40 /* Disable the backup domain write protection */
41 /* the protection is enable at each reset by hardware */
42 /* And must be disable by software */
43 setbits_le32(PWR_CR1, PWR_CR1_DBP);
45 while (!(readl(PWR_CR1) & PWR_CR1_DBP))
48 /* If RTC clock isn't enable so this is a cold boot then we need
49 * to reset the backup domain
51 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
52 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
53 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
55 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
58 /* allow non secure access in Write/Read for all peripheral */
59 writel(GENMASK(25, 0), ETZPC_DECPROT0);
61 /* Open SYSRAM for no secure access */
62 writel(0x0, ETZPC_TZMA1_SIZE);
64 /* enable TZC1 TZC2 clock */
65 writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
67 /* Region 0 set to no access by default */
68 /* bit 0 / 16 => nsaid0 read/write Enable
69 * bit 1 / 17 => nsaid1 read/write Enable
71 * bit 15 / 31 => nsaid15 read/write Enable
73 writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
74 /* bit 30 / 31 => Secure Global Enable : write/read */
75 /* bit 0 / 1 => Region Enable for filter 0/1 */
76 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
78 /* Enable Filter 0 and 1 */
79 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
81 /* RCC trust zone deactivated */
82 writel(0x0, RCC_TZCR);
84 /* TAMP: deactivate the internal tamper
85 * Bit 23 ITAMP8E: monotonic counter overflow
86 * Bit 20 ITAMP5E: RTC calendar overflow
87 * Bit 19 ITAMP4E: HSE monitoring
88 * Bit 18 ITAMP3E: LSE monitoring
89 * Bit 16 ITAMP1E: RTC power domain supply monitoring
91 writel(0x0, TAMP_CR1);
97 static void dbgmcu_init(void)
99 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
101 /* Freeze IWDG2 if Cortex-A7 is in debug mode */
102 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
104 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
106 int arch_cpu_init(void)
108 /* early armv7 timer init: needed for polling */
111 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
120 void enable_caches(void)
122 /* Enable D-cache. I-cache is already enabled in start.S */
126 #if defined(CONFIG_DISPLAY_CPUINFO)
127 int print_cpuinfo(void)
129 printf("CPU: STM32MP15x\n");
133 #endif /* CONFIG_DISPLAY_CPUINFO */
135 void reset_cpu(ulong addr)