1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
8 #include <debug_uart.h>
12 #include <asm/arch/stm32.h>
13 #include <asm/arch/sys_proto.h>
14 #include <dm/device.h>
15 #include <dm/uclass.h>
18 #define RCC_TZCR (STM32_RCC_BASE + 0x00)
19 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
20 #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
21 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
22 #define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
23 #define RCC_BDCR_VSWRST BIT(31)
24 #define RCC_BDCR_RTCSRC GENMASK(17, 16)
25 #define RCC_DBGCFGR_DBGCKEN BIT(8)
27 /* Security register */
28 #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
29 #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
31 #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
32 #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
33 #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
35 #define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
37 #define PWR_CR1 (STM32_PWR_BASE + 0x00)
38 #define PWR_MCUCR (STM32_PWR_BASE + 0x14)
39 #define PWR_CR1_DBP BIT(8)
40 #define PWR_MCUCR_SBF BIT(6)
43 #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
44 #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
45 #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
46 #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
47 #define DBGMCU_IDC_DEV_ID_SHIFT 0
48 #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
49 #define DBGMCU_IDC_REV_ID_SHIFT 16
52 #define GPIOZ_SECCFGR 0x54004030
54 /* boot interface from Bootrom
55 * - boot instance = bit 31:16
56 * - boot device = bit 15:0
58 #define BOOTROM_PARAM_ADDR 0x2FFC0078
59 #define BOOTROM_MODE_MASK GENMASK(15, 0)
60 #define BOOTROM_MODE_SHIFT 0
61 #define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
62 #define BOOTROM_INSTANCE_SHIFT 16
64 /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
66 #define RPN_MASK GENMASK(7, 0)
68 /* Package = bit 27:29 of OTP16
69 * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
70 * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
71 * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
72 * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
76 #define PKG_MASK GENMASK(2, 0)
78 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
79 #ifndef CONFIG_TFABOOT
80 static void security_init(void)
82 /* Disable the backup domain write protection */
83 /* the protection is enable at each reset by hardware */
84 /* And must be disable by software */
85 setbits_le32(PWR_CR1, PWR_CR1_DBP);
87 while (!(readl(PWR_CR1) & PWR_CR1_DBP))
90 /* If RTC clock isn't enable so this is a cold boot then we need
91 * to reset the backup domain
93 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
94 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
95 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
97 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
100 /* allow non secure access in Write/Read for all peripheral */
101 writel(GENMASK(25, 0), ETZPC_DECPROT0);
103 /* Open SYSRAM for no secure access */
104 writel(0x0, ETZPC_TZMA1_SIZE);
106 /* enable TZC1 TZC2 clock */
107 writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
109 /* Region 0 set to no access by default */
110 /* bit 0 / 16 => nsaid0 read/write Enable
111 * bit 1 / 17 => nsaid1 read/write Enable
113 * bit 15 / 31 => nsaid15 read/write Enable
115 writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
116 /* bit 30 / 31 => Secure Global Enable : write/read */
117 /* bit 0 / 1 => Region Enable for filter 0/1 */
118 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
120 /* Enable Filter 0 and 1 */
121 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
123 /* RCC trust zone deactivated */
124 writel(0x0, RCC_TZCR);
126 /* TAMP: deactivate the internal tamper
127 * Bit 23 ITAMP8E: monotonic counter overflow
128 * Bit 20 ITAMP5E: RTC calendar overflow
129 * Bit 19 ITAMP4E: HSE monitoring
130 * Bit 18 ITAMP3E: LSE monitoring
131 * Bit 16 ITAMP1E: RTC power domain supply monitoring
133 writel(0x0, TAMP_CR1);
135 /* GPIOZ: deactivate the security */
136 writel(BIT(0), RCC_MP_AHB5ENSETR);
137 writel(0x0, GPIOZ_SECCFGR);
139 #endif /* CONFIG_TFABOOT */
144 static void dbgmcu_init(void)
146 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
148 /* Freeze IWDG2 if Cortex-A7 is in debug mode */
149 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
151 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
153 #if !defined(CONFIG_TFABOOT) && \
154 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
155 /* get bootmode from ROM code boot context: saved in TAMP register */
156 static void update_bootmode(void)
159 u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
160 u32 bootrom_device, bootrom_instance;
162 /* enable TAMP clock = RTCAPBEN */
163 writel(BIT(8), RCC_MP_APB5ENSETR);
165 /* read bootrom context */
167 (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
169 (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
171 ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
172 ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
175 /* save the boot mode in TAMP backup register */
176 clrsetbits_le32(TAMP_BOOT_CONTEXT,
178 boot_mode << TAMP_BOOT_MODE_SHIFT);
182 u32 get_bootmode(void)
184 /* read bootmode from TAMP backup register */
185 return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
186 TAMP_BOOT_MODE_SHIFT;
192 int arch_cpu_init(void)
196 /* early armv7 timer init: needed for polling */
199 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
201 #ifndef CONFIG_TFABOOT
205 /* Reset Coprocessor state unless it wakes up from Standby power mode */
206 if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
207 writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
208 writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
212 boot_mode = get_bootmode();
214 if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
215 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
216 #if defined(CONFIG_DEBUG_UART) && \
217 !defined(CONFIG_TFABOOT) && \
218 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
226 void enable_caches(void)
228 /* Enable D-cache. I-cache is already enabled in start.S */
232 static u32 read_idc(void)
234 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
236 return readl(DBGMCU_IDC);
239 u32 get_cpu_dev(void)
241 return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
244 u32 get_cpu_rev(void)
246 return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
249 static u32 get_otp(int index, int shift, int mask)
255 ret = uclass_get_device_by_driver(UCLASS_MISC,
256 DM_GET_DRIVER(stm32mp_bsec),
260 ret = misc_read(dev, STM32_BSEC_SHADOW(index),
263 return (otp >> shift) & mask;
266 /* Get Device Part Number (RPN) from OTP */
267 static u32 get_cpu_rpn(void)
269 return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
272 u32 get_cpu_type(void)
274 return (get_cpu_dev() << 16) | get_cpu_rpn();
277 /* Get Package options from OTP */
278 u32 get_cpu_package(void)
280 return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
283 void get_soc_name(char name[SOC_NAME_SIZE])
285 char *cpu_s, *cpu_r, *pkg;
287 /* MPUs Part Numbers */
288 switch (get_cpu_type()) {
289 case CPU_STM32MP157Fxx:
292 case CPU_STM32MP157Dxx:
295 case CPU_STM32MP157Cxx:
298 case CPU_STM32MP157Axx:
301 case CPU_STM32MP153Fxx:
304 case CPU_STM32MP153Dxx:
307 case CPU_STM32MP153Cxx:
310 case CPU_STM32MP153Axx:
313 case CPU_STM32MP151Fxx:
316 case CPU_STM32MP151Dxx:
319 case CPU_STM32MP151Cxx:
322 case CPU_STM32MP151Axx:
331 switch (get_cpu_package()) {
338 case PKG_AC_TFBGA361:
341 case PKG_AD_TFBGA257:
350 switch (get_cpu_rev()) {
365 snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r);
368 #if defined(CONFIG_DISPLAY_CPUINFO)
369 int print_cpuinfo(void)
371 char name[SOC_NAME_SIZE];
374 printf("CPU: %s\n", name);
378 #endif /* CONFIG_DISPLAY_CPUINFO */
380 static void setup_boot_mode(void)
382 const u32 serial_addr[] = {
393 u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
395 (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
396 unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
397 u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
401 pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
402 __func__, boot_ctx, boot_mode, instance, forced_mode);
403 switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
404 case BOOT_SERIAL_UART:
405 if (instance > ARRAY_SIZE(serial_addr))
407 /* serial : search associated alias in devicetree */
408 sprintf(cmd, "serial@%x", serial_addr[instance]);
409 if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev))
411 if (fdtdec_get_alias_seq(gd->fdt_blob, "serial",
412 dev_of_offset(dev), &alias))
414 sprintf(cmd, "%d", alias);
415 env_set("boot_device", "serial");
416 env_set("boot_instance", cmd);
418 /* restore console on uart when not used */
419 if (gd->cur_serial_dev != dev) {
420 gd->flags &= ~(GD_FLG_SILENT |
421 GD_FLG_DISABLE_CONSOLE);
422 printf("serial boot with console enabled!\n");
425 case BOOT_SERIAL_USB:
426 env_set("boot_device", "usb");
427 env_set("boot_instance", "0");
430 case BOOT_FLASH_EMMC:
431 sprintf(cmd, "%d", instance);
432 env_set("boot_device", "mmc");
433 env_set("boot_instance", cmd);
435 case BOOT_FLASH_NAND:
436 env_set("boot_device", "nand");
437 env_set("boot_instance", "0");
439 case BOOT_FLASH_SPINAND:
440 env_set("boot_device", "spi-nand");
441 env_set("boot_instance", "0");
444 env_set("boot_device", "nor");
445 env_set("boot_instance", "0");
448 pr_debug("unexpected boot mode = %x\n", boot_mode);
452 switch (forced_mode) {
454 printf("Enter fastboot!\n");
455 env_set("preboot", "env set preboot; fastboot 0");
458 env_set("boot_device", "usb");
459 env_set("boot_instance", "0");
464 printf("Enter UMS!\n");
465 instance = forced_mode - BOOT_UMS_MMC0;
466 sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
467 env_set("preboot", cmd);
470 env_set("preboot", "env set preboot; run altbootcmd");
475 pr_debug("unexpected forced boot mode = %x\n", forced_mode);
479 /* clear TAMP for next reboot */
480 clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
484 * If there is no MAC address in the environment, then it will be initialized
485 * (silently) from the value in the OTP.
487 __weak int setup_mac_address(void)
489 #if defined(CONFIG_NET)
496 /* MAC already in environment */
497 if (eth_env_get_enetaddr("ethaddr", enetaddr))
500 ret = uclass_get_device_by_driver(UCLASS_MISC,
501 DM_GET_DRIVER(stm32mp_bsec),
506 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC),
511 for (i = 0; i < 6; i++)
512 enetaddr[i] = ((uint8_t *)&otp)[i];
514 if (!is_valid_ethaddr(enetaddr)) {
515 pr_err("invalid MAC address in OTP %pM\n", enetaddr);
518 pr_debug("OTP MAC address = %pM\n", enetaddr);
519 ret = !eth_env_set_enetaddr("ethaddr", enetaddr);
521 pr_err("Failed to set mac address %pM from OTP: %d\n",
528 static int setup_serial_number(void)
530 char serial_string[25];
531 u32 otp[3] = {0, 0, 0 };
535 if (env_get("serial#"))
538 ret = uclass_get_device_by_driver(UCLASS_MISC,
539 DM_GET_DRIVER(stm32mp_bsec),
544 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
549 sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
550 env_set("serial#", serial_string);
555 int arch_misc_init(void)
559 setup_serial_number();