1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
8 #include <debug_uart.h>
15 #include <asm/arch/stm32.h>
16 #include <asm/arch/sys_proto.h>
17 #include <dm/device.h>
18 #include <dm/uclass.h>
21 #define RCC_TZCR (STM32_RCC_BASE + 0x00)
22 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
23 #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
24 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
25 #define RCC_MP_AHB5ENSETR (STM32_RCC_BASE + 0x0210)
26 #define RCC_BDCR_VSWRST BIT(31)
27 #define RCC_BDCR_RTCSRC GENMASK(17, 16)
28 #define RCC_DBGCFGR_DBGCKEN BIT(8)
30 /* Security register */
31 #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
32 #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
34 #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
35 #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
36 #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
38 #define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
40 #define PWR_CR1 (STM32_PWR_BASE + 0x00)
41 #define PWR_MCUCR (STM32_PWR_BASE + 0x14)
42 #define PWR_CR1_DBP BIT(8)
43 #define PWR_MCUCR_SBF BIT(6)
46 #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
47 #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
48 #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
49 #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
50 #define DBGMCU_IDC_DEV_ID_SHIFT 0
51 #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
52 #define DBGMCU_IDC_REV_ID_SHIFT 16
55 #define GPIOZ_SECCFGR 0x54004030
57 /* boot interface from Bootrom
58 * - boot instance = bit 31:16
59 * - boot device = bit 15:0
61 #define BOOTROM_PARAM_ADDR 0x2FFC0078
62 #define BOOTROM_MODE_MASK GENMASK(15, 0)
63 #define BOOTROM_MODE_SHIFT 0
64 #define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
65 #define BOOTROM_INSTANCE_SHIFT 16
67 /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
69 #define RPN_MASK GENMASK(7, 0)
71 /* Package = bit 27:29 of OTP16
72 * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
73 * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
74 * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
75 * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
79 #define PKG_MASK GENMASK(2, 0)
82 * early TLB into the .data section so that it not get cleared
83 * with 16kB allignment (see TTBR0_BASE_ADDR_MASK)
85 u8 early_tlb[PGTABLE_SIZE] __section(".data") __aligned(0x4000);
87 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
88 #ifndef CONFIG_TFABOOT
89 static void security_init(void)
91 /* Disable the backup domain write protection */
92 /* the protection is enable at each reset by hardware */
93 /* And must be disable by software */
94 setbits_le32(PWR_CR1, PWR_CR1_DBP);
96 while (!(readl(PWR_CR1) & PWR_CR1_DBP))
99 /* If RTC clock isn't enable so this is a cold boot then we need
100 * to reset the backup domain
102 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
103 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
104 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
106 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
109 /* allow non secure access in Write/Read for all peripheral */
110 writel(GENMASK(25, 0), ETZPC_DECPROT0);
112 /* Open SYSRAM for no secure access */
113 writel(0x0, ETZPC_TZMA1_SIZE);
115 /* enable TZC1 TZC2 clock */
116 writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
118 /* Region 0 set to no access by default */
119 /* bit 0 / 16 => nsaid0 read/write Enable
120 * bit 1 / 17 => nsaid1 read/write Enable
122 * bit 15 / 31 => nsaid15 read/write Enable
124 writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
125 /* bit 30 / 31 => Secure Global Enable : write/read */
126 /* bit 0 / 1 => Region Enable for filter 0/1 */
127 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
129 /* Enable Filter 0 and 1 */
130 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
132 /* RCC trust zone deactivated */
133 writel(0x0, RCC_TZCR);
135 /* TAMP: deactivate the internal tamper
136 * Bit 23 ITAMP8E: monotonic counter overflow
137 * Bit 20 ITAMP5E: RTC calendar overflow
138 * Bit 19 ITAMP4E: HSE monitoring
139 * Bit 18 ITAMP3E: LSE monitoring
140 * Bit 16 ITAMP1E: RTC power domain supply monitoring
142 writel(0x0, TAMP_CR1);
144 /* GPIOZ: deactivate the security */
145 writel(BIT(0), RCC_MP_AHB5ENSETR);
146 writel(0x0, GPIOZ_SECCFGR);
148 #endif /* CONFIG_TFABOOT */
153 static void dbgmcu_init(void)
155 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
157 /* Freeze IWDG2 if Cortex-A7 is in debug mode */
158 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
160 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
162 #if !defined(CONFIG_TFABOOT) && \
163 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
164 /* get bootmode from ROM code boot context: saved in TAMP register */
165 static void update_bootmode(void)
168 u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
169 u32 bootrom_device, bootrom_instance;
171 /* enable TAMP clock = RTCAPBEN */
172 writel(BIT(8), RCC_MP_APB5ENSETR);
174 /* read bootrom context */
176 (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
178 (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
180 ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
181 ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
184 /* save the boot mode in TAMP backup register */
185 clrsetbits_le32(TAMP_BOOT_CONTEXT,
187 boot_mode << TAMP_BOOT_MODE_SHIFT);
191 u32 get_bootmode(void)
193 /* read bootmode from TAMP backup register */
194 return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
195 TAMP_BOOT_MODE_SHIFT;
199 * initialize the MMU and activate cache in SPL or in U-Boot pre-reloc stage
200 * MMU/TLB is updated in enable_caches() for U-Boot after relocation
201 * or is deactivated in U-Boot entry function start.S::cpu_init_cp15
203 static void early_enable_caches(void)
205 /* I-cache is already enabled in start.S: cpu_init_cp15 */
207 if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF))
210 gd->arch.tlb_size = PGTABLE_SIZE;
211 gd->arch.tlb_addr = (unsigned long)&early_tlb;
215 if (IS_ENABLED(CONFIG_SPL_BUILD))
216 mmu_set_region_dcache_behaviour(STM32_SYSRAM_BASE,
218 DCACHE_DEFAULT_OPTION);
220 mmu_set_region_dcache_behaviour(STM32_DDR_BASE, STM32_DDR_SIZE,
221 DCACHE_DEFAULT_OPTION);
227 int arch_cpu_init(void)
231 early_enable_caches();
233 /* early armv7 timer init: needed for polling */
236 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
238 #ifndef CONFIG_TFABOOT
242 /* Reset Coprocessor state unless it wakes up from Standby power mode */
243 if (!(readl(PWR_MCUCR) & PWR_MCUCR_SBF)) {
244 writel(TAMP_COPRO_STATE_OFF, TAMP_COPRO_STATE);
245 writel(0, TAMP_COPRO_RSC_TBL_ADDRESS);
249 boot_mode = get_bootmode();
251 if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
252 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
253 #if defined(CONFIG_DEBUG_UART) && \
254 !defined(CONFIG_TFABOOT) && \
255 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
263 void enable_caches(void)
265 /* I-cache is already enabled in start.S: icache_enable() not needed */
267 /* deactivate the data cache, early enabled in arch_cpu_init() */
270 * update MMU after relocation and enable the data cache
271 * warning: the TLB location udpated in board_f.c::reserve_mmu
276 static u32 read_idc(void)
278 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
280 return readl(DBGMCU_IDC);
283 u32 get_cpu_dev(void)
285 return (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
288 u32 get_cpu_rev(void)
290 return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
293 static u32 get_otp(int index, int shift, int mask)
299 ret = uclass_get_device_by_driver(UCLASS_MISC,
300 DM_GET_DRIVER(stm32mp_bsec),
304 ret = misc_read(dev, STM32_BSEC_SHADOW(index),
307 return (otp >> shift) & mask;
310 /* Get Device Part Number (RPN) from OTP */
311 static u32 get_cpu_rpn(void)
313 return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
316 u32 get_cpu_type(void)
318 return (get_cpu_dev() << 16) | get_cpu_rpn();
321 /* Get Package options from OTP */
322 u32 get_cpu_package(void)
324 return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
327 void get_soc_name(char name[SOC_NAME_SIZE])
329 char *cpu_s, *cpu_r, *pkg;
331 /* MPUs Part Numbers */
332 switch (get_cpu_type()) {
333 case CPU_STM32MP157Fxx:
336 case CPU_STM32MP157Dxx:
339 case CPU_STM32MP157Cxx:
342 case CPU_STM32MP157Axx:
345 case CPU_STM32MP153Fxx:
348 case CPU_STM32MP153Dxx:
351 case CPU_STM32MP153Cxx:
354 case CPU_STM32MP153Axx:
357 case CPU_STM32MP151Fxx:
360 case CPU_STM32MP151Dxx:
363 case CPU_STM32MP151Cxx:
366 case CPU_STM32MP151Axx:
375 switch (get_cpu_package()) {
382 case PKG_AC_TFBGA361:
385 case PKG_AD_TFBGA257:
394 switch (get_cpu_rev()) {
409 snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, pkg, cpu_r);
412 #if defined(CONFIG_DISPLAY_CPUINFO)
413 int print_cpuinfo(void)
415 char name[SOC_NAME_SIZE];
418 printf("CPU: %s\n", name);
422 #endif /* CONFIG_DISPLAY_CPUINFO */
424 static void setup_boot_mode(void)
426 const u32 serial_addr[] = {
437 u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
439 (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
440 unsigned int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
441 u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
445 pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
446 __func__, boot_ctx, boot_mode, instance, forced_mode);
447 switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
448 case BOOT_SERIAL_UART:
449 if (instance > ARRAY_SIZE(serial_addr))
451 /* serial : search associated alias in devicetree */
452 sprintf(cmd, "serial@%x", serial_addr[instance]);
453 if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev))
455 if (fdtdec_get_alias_seq(gd->fdt_blob, "serial",
456 dev_of_offset(dev), &alias))
458 sprintf(cmd, "%d", alias);
459 env_set("boot_device", "serial");
460 env_set("boot_instance", cmd);
462 /* restore console on uart when not used */
463 if (gd->cur_serial_dev != dev) {
464 gd->flags &= ~(GD_FLG_SILENT |
465 GD_FLG_DISABLE_CONSOLE);
466 printf("serial boot with console enabled!\n");
469 case BOOT_SERIAL_USB:
470 env_set("boot_device", "usb");
471 env_set("boot_instance", "0");
474 case BOOT_FLASH_EMMC:
475 sprintf(cmd, "%d", instance);
476 env_set("boot_device", "mmc");
477 env_set("boot_instance", cmd);
479 case BOOT_FLASH_NAND:
480 env_set("boot_device", "nand");
481 env_set("boot_instance", "0");
483 case BOOT_FLASH_SPINAND:
484 env_set("boot_device", "spi-nand");
485 env_set("boot_instance", "0");
488 env_set("boot_device", "nor");
489 env_set("boot_instance", "0");
492 pr_debug("unexpected boot mode = %x\n", boot_mode);
496 switch (forced_mode) {
498 printf("Enter fastboot!\n");
499 env_set("preboot", "env set preboot; fastboot 0");
502 env_set("boot_device", "usb");
503 env_set("boot_instance", "0");
508 printf("Enter UMS!\n");
509 instance = forced_mode - BOOT_UMS_MMC0;
510 sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
511 env_set("preboot", cmd);
514 env_set("preboot", "env set preboot; run altbootcmd");
519 pr_debug("unexpected forced boot mode = %x\n", forced_mode);
523 /* clear TAMP for next reboot */
524 clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
528 * If there is no MAC address in the environment, then it will be initialized
529 * (silently) from the value in the OTP.
531 __weak int setup_mac_address(void)
533 #if defined(CONFIG_NET)
540 /* MAC already in environment */
541 if (eth_env_get_enetaddr("ethaddr", enetaddr))
544 ret = uclass_get_device_by_driver(UCLASS_MISC,
545 DM_GET_DRIVER(stm32mp_bsec),
550 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_MAC),
555 for (i = 0; i < 6; i++)
556 enetaddr[i] = ((uint8_t *)&otp)[i];
558 if (!is_valid_ethaddr(enetaddr)) {
559 pr_err("invalid MAC address in OTP %pM\n", enetaddr);
562 pr_debug("OTP MAC address = %pM\n", enetaddr);
563 ret = !eth_env_set_enetaddr("ethaddr", enetaddr);
565 pr_err("Failed to set mac address %pM from OTP: %d\n",
572 static int setup_serial_number(void)
574 char serial_string[25];
575 u32 otp[3] = {0, 0, 0 };
579 if (env_get("serial#"))
582 ret = uclass_get_device_by_driver(UCLASS_MISC,
583 DM_GET_DRIVER(stm32mp_bsec),
588 ret = misc_read(dev, STM32_BSEC_SHADOW(BSEC_OTP_SERIAL),
593 sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
594 env_set("serial#", serial_string);
599 int arch_misc_init(void)
603 setup_serial_number();