1 // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
3 * Copyright (C) 2018, STMicroelectronics - All Rights Reserved
7 #include <debug_uart.h>
8 #include <environment.h>
11 #include <asm/arch/stm32.h>
12 #include <asm/arch/sys_proto.h>
13 #include <dm/device.h>
14 #include <dm/uclass.h>
17 #define RCC_TZCR (STM32_RCC_BASE + 0x00)
18 #define RCC_DBGCFGR (STM32_RCC_BASE + 0x080C)
19 #define RCC_BDCR (STM32_RCC_BASE + 0x0140)
20 #define RCC_MP_APB5ENSETR (STM32_RCC_BASE + 0x0208)
21 #define RCC_BDCR_VSWRST BIT(31)
22 #define RCC_BDCR_RTCSRC GENMASK(17, 16)
23 #define RCC_DBGCFGR_DBGCKEN BIT(8)
25 /* Security register */
26 #define ETZPC_TZMA1_SIZE (STM32_ETZPC_BASE + 0x04)
27 #define ETZPC_DECPROT0 (STM32_ETZPC_BASE + 0x10)
29 #define TZC_GATE_KEEPER (STM32_TZC_BASE + 0x008)
30 #define TZC_REGION_ATTRIBUTE0 (STM32_TZC_BASE + 0x110)
31 #define TZC_REGION_ID_ACCESS0 (STM32_TZC_BASE + 0x114)
33 #define TAMP_CR1 (STM32_TAMP_BASE + 0x00)
35 #define PWR_CR1 (STM32_PWR_BASE + 0x00)
36 #define PWR_CR1_DBP BIT(8)
39 #define DBGMCU_IDC (STM32_DBGMCU_BASE + 0x00)
40 #define DBGMCU_APB4FZ1 (STM32_DBGMCU_BASE + 0x2C)
41 #define DBGMCU_APB4FZ1_IWDG2 BIT(2)
42 #define DBGMCU_IDC_DEV_ID_MASK GENMASK(11, 0)
43 #define DBGMCU_IDC_DEV_ID_SHIFT 0
44 #define DBGMCU_IDC_REV_ID_MASK GENMASK(31, 16)
45 #define DBGMCU_IDC_REV_ID_SHIFT 16
47 /* boot interface from Bootrom
48 * - boot instance = bit 31:16
49 * - boot device = bit 15:0
51 #define BOOTROM_PARAM_ADDR 0x2FFC0078
52 #define BOOTROM_MODE_MASK GENMASK(15, 0)
53 #define BOOTROM_MODE_SHIFT 0
54 #define BOOTROM_INSTANCE_MASK GENMASK(31, 16)
55 #define BOOTROM_INSTANCE_SHIFT 16
58 #define BSEC_OTP_RPN 1
59 #define BSEC_OTP_SERIAL 13
60 #define BSEC_OTP_PKG 16
61 #define BSEC_OTP_MAC 57
63 /* Device Part Number (RPN) = OTP_DATA1 lower 8 bits */
65 #define RPN_MASK GENMASK(7, 0)
67 /* Package = bit 27:29 of OTP16
68 * - 100: LBGA448 (FFI) => AA = LFBGA 18x18mm 448 balls p. 0.8mm
69 * - 011: LBGA354 (LCI) => AB = LFBGA 16x16mm 359 balls p. 0.8mm
70 * - 010: TFBGA361 (FFC) => AC = TFBGA 12x12mm 361 balls p. 0.5mm
71 * - 001: TFBGA257 (LCC) => AD = TFBGA 10x10mm 257 balls p. 0.5mm
75 #define PKG_MASK GENMASK(2, 0)
77 #define PKG_AA_LBGA448 4
78 #define PKG_AB_LBGA354 3
79 #define PKG_AC_TFBGA361 2
80 #define PKG_AD_TFBGA257 1
82 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
83 #ifndef CONFIG_STM32MP1_TRUSTED
84 static void security_init(void)
86 /* Disable the backup domain write protection */
87 /* the protection is enable at each reset by hardware */
88 /* And must be disable by software */
89 setbits_le32(PWR_CR1, PWR_CR1_DBP);
91 while (!(readl(PWR_CR1) & PWR_CR1_DBP))
94 /* If RTC clock isn't enable so this is a cold boot then we need
95 * to reset the backup domain
97 if (!(readl(RCC_BDCR) & RCC_BDCR_RTCSRC)) {
98 setbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
99 while (!(readl(RCC_BDCR) & RCC_BDCR_VSWRST))
101 clrbits_le32(RCC_BDCR, RCC_BDCR_VSWRST);
104 /* allow non secure access in Write/Read for all peripheral */
105 writel(GENMASK(25, 0), ETZPC_DECPROT0);
107 /* Open SYSRAM for no secure access */
108 writel(0x0, ETZPC_TZMA1_SIZE);
110 /* enable TZC1 TZC2 clock */
111 writel(BIT(11) | BIT(12), RCC_MP_APB5ENSETR);
113 /* Region 0 set to no access by default */
114 /* bit 0 / 16 => nsaid0 read/write Enable
115 * bit 1 / 17 => nsaid1 read/write Enable
117 * bit 15 / 31 => nsaid15 read/write Enable
119 writel(0xFFFFFFFF, TZC_REGION_ID_ACCESS0);
120 /* bit 30 / 31 => Secure Global Enable : write/read */
121 /* bit 0 / 1 => Region Enable for filter 0/1 */
122 writel(BIT(0) | BIT(1) | BIT(30) | BIT(31), TZC_REGION_ATTRIBUTE0);
124 /* Enable Filter 0 and 1 */
125 setbits_le32(TZC_GATE_KEEPER, BIT(0) | BIT(1));
127 /* RCC trust zone deactivated */
128 writel(0x0, RCC_TZCR);
130 /* TAMP: deactivate the internal tamper
131 * Bit 23 ITAMP8E: monotonic counter overflow
132 * Bit 20 ITAMP5E: RTC calendar overflow
133 * Bit 19 ITAMP4E: HSE monitoring
134 * Bit 18 ITAMP3E: LSE monitoring
135 * Bit 16 ITAMP1E: RTC power domain supply monitoring
137 writel(0x0, TAMP_CR1);
139 #endif /* CONFIG_STM32MP1_TRUSTED */
144 static void dbgmcu_init(void)
146 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
148 /* Freeze IWDG2 if Cortex-A7 is in debug mode */
149 setbits_le32(DBGMCU_APB4FZ1, DBGMCU_APB4FZ1_IWDG2);
151 #endif /* !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) */
153 #if !defined(CONFIG_STM32MP1_TRUSTED) && \
154 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
155 /* get bootmode from ROM code boot context: saved in TAMP register */
156 static void update_bootmode(void)
159 u32 bootrom_itf = readl(BOOTROM_PARAM_ADDR);
160 u32 bootrom_device, bootrom_instance;
162 /* enable TAMP clock = RTCAPBEN */
163 writel(BIT(8), RCC_MP_APB5ENSETR);
165 /* read bootrom context */
167 (bootrom_itf & BOOTROM_MODE_MASK) >> BOOTROM_MODE_SHIFT;
169 (bootrom_itf & BOOTROM_INSTANCE_MASK) >> BOOTROM_INSTANCE_SHIFT;
171 ((bootrom_device << BOOT_TYPE_SHIFT) & BOOT_TYPE_MASK) |
172 ((bootrom_instance << BOOT_INSTANCE_SHIFT) &
175 /* save the boot mode in TAMP backup register */
176 clrsetbits_le32(TAMP_BOOT_CONTEXT,
178 boot_mode << TAMP_BOOT_MODE_SHIFT);
182 u32 get_bootmode(void)
184 /* read bootmode from TAMP backup register */
185 return (readl(TAMP_BOOT_CONTEXT) & TAMP_BOOT_MODE_MASK) >>
186 TAMP_BOOT_MODE_SHIFT;
192 int arch_cpu_init(void)
196 /* early armv7 timer init: needed for polling */
199 #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)
201 #ifndef CONFIG_STM32MP1_TRUSTED
207 boot_mode = get_bootmode();
209 if ((boot_mode & TAMP_BOOT_DEVICE_MASK) == BOOT_SERIAL_UART)
210 gd->flags |= GD_FLG_SILENT | GD_FLG_DISABLE_CONSOLE;
211 #if defined(CONFIG_DEBUG_UART) && \
212 !defined(CONFIG_STM32MP1_TRUSTED) && \
213 (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD))
221 void enable_caches(void)
223 /* Enable D-cache. I-cache is already enabled in start.S */
227 static u32 read_idc(void)
229 setbits_le32(RCC_DBGCFGR, RCC_DBGCFGR_DBGCKEN);
231 return readl(DBGMCU_IDC);
234 u32 get_cpu_rev(void)
236 return (read_idc() & DBGMCU_IDC_REV_ID_MASK) >> DBGMCU_IDC_REV_ID_SHIFT;
239 static u32 get_otp(int index, int shift, int mask)
245 ret = uclass_get_device_by_driver(UCLASS_MISC,
246 DM_GET_DRIVER(stm32mp_bsec),
250 ret = misc_read(dev, STM32_BSEC_SHADOW(index),
253 return (otp >> shift) & mask;
256 /* Get Device Part Number (RPN) from OTP */
257 static u32 get_cpu_rpn(void)
259 return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK);
262 u32 get_cpu_type(void)
266 id = (read_idc() & DBGMCU_IDC_DEV_ID_MASK) >> DBGMCU_IDC_DEV_ID_SHIFT;
268 return (id << 16) | get_cpu_rpn();
271 /* Get Package options from OTP */
272 static u32 get_cpu_package(void)
274 return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK);
277 #if defined(CONFIG_DISPLAY_CPUINFO)
278 int print_cpuinfo(void)
280 char *cpu_s, *cpu_r, *pkg;
282 /* MPUs Part Numbers */
283 switch (get_cpu_type()) {
284 case CPU_STM32MP157Cxx:
287 case CPU_STM32MP157Axx:
290 case CPU_STM32MP153Cxx:
293 case CPU_STM32MP153Axx:
296 case CPU_STM32MP151Cxx:
299 case CPU_STM32MP151Axx:
308 switch (get_cpu_package()) {
315 case PKG_AC_TFBGA361:
318 case PKG_AD_TFBGA257:
327 switch (get_cpu_rev()) {
339 printf("CPU: STM32MP%s%s Rev.%s\n", cpu_s, pkg, cpu_r);
343 #endif /* CONFIG_DISPLAY_CPUINFO */
345 static void setup_boot_mode(void)
347 const u32 serial_addr[] = {
358 u32 boot_ctx = readl(TAMP_BOOT_CONTEXT);
360 (boot_ctx & TAMP_BOOT_MODE_MASK) >> TAMP_BOOT_MODE_SHIFT;
361 int instance = (boot_mode & TAMP_BOOT_INSTANCE_MASK) - 1;
362 u32 forced_mode = (boot_ctx & TAMP_BOOT_FORCED_MASK);
366 pr_debug("%s: boot_ctx=0x%x => boot_mode=%x, instance=%d forced=%x\n",
367 __func__, boot_ctx, boot_mode, instance, forced_mode);
368 switch (boot_mode & TAMP_BOOT_DEVICE_MASK) {
369 case BOOT_SERIAL_UART:
370 if (instance > ARRAY_SIZE(serial_addr))
372 /* serial : search associated alias in devicetree */
373 sprintf(cmd, "serial@%x", serial_addr[instance]);
374 if (uclass_get_device_by_name(UCLASS_SERIAL, cmd, &dev))
376 if (fdtdec_get_alias_seq(gd->fdt_blob, "serial",
377 dev_of_offset(dev), &alias))
379 sprintf(cmd, "%d", alias);
380 env_set("boot_device", "serial");
381 env_set("boot_instance", cmd);
383 /* restore console on uart when not used */
384 if (gd->cur_serial_dev != dev) {
385 gd->flags &= ~(GD_FLG_SILENT |
386 GD_FLG_DISABLE_CONSOLE);
387 printf("serial boot with console enabled!\n");
390 case BOOT_SERIAL_USB:
391 env_set("boot_device", "usb");
392 env_set("boot_instance", "0");
395 case BOOT_FLASH_EMMC:
396 sprintf(cmd, "%d", instance);
397 env_set("boot_device", "mmc");
398 env_set("boot_instance", cmd);
400 case BOOT_FLASH_NAND:
401 env_set("boot_device", "nand");
402 env_set("boot_instance", "0");
405 env_set("boot_device", "nor");
406 env_set("boot_instance", "0");
409 pr_debug("unexpected boot mode = %x\n", boot_mode);
413 switch (forced_mode) {
415 printf("Enter fastboot!\n");
416 env_set("preboot", "env set preboot; fastboot 0");
419 env_set("boot_device", "usb");
420 env_set("boot_instance", "0");
425 printf("Enter UMS!\n");
426 instance = forced_mode - BOOT_UMS_MMC0;
427 sprintf(cmd, "env set preboot; ums 0 mmc %d", instance);
428 env_set("preboot", cmd);
431 env_set("preboot", "env set preboot; run altbootcmd");
436 pr_debug("unexpected forced boot mode = %x\n", forced_mode);
440 /* clear TAMP for next reboot */
441 clrsetbits_le32(TAMP_BOOT_CONTEXT, TAMP_BOOT_FORCED_MASK, BOOT_NORMAL);
445 * If there is no MAC address in the environment, then it will be initialized
446 * (silently) from the value in the OTP.
448 static int setup_mac_address(void)
450 #if defined(CONFIG_NET)
457 /* MAC already in environment */
458 if (eth_env_get_enetaddr("ethaddr", enetaddr))
461 ret = uclass_get_device_by_driver(UCLASS_MISC,
462 DM_GET_DRIVER(stm32mp_bsec),
467 ret = misc_read(dev, BSEC_OTP_MAC * 4 + STM32_BSEC_OTP_OFFSET,
472 for (i = 0; i < 6; i++)
473 enetaddr[i] = ((uint8_t *)&otp)[i];
475 if (!is_valid_ethaddr(enetaddr)) {
476 pr_err("invalid MAC address in OTP %pM", enetaddr);
479 pr_debug("OTP MAC address = %pM\n", enetaddr);
480 ret = !eth_env_set_enetaddr("ethaddr", enetaddr);
482 pr_err("Failed to set mac address %pM from OTP: %d\n",
489 static int setup_serial_number(void)
491 char serial_string[25];
492 u32 otp[3] = {0, 0, 0 };
496 if (env_get("serial#"))
499 ret = uclass_get_device_by_driver(UCLASS_MISC,
500 DM_GET_DRIVER(stm32mp_bsec),
505 ret = misc_read(dev, BSEC_OTP_SERIAL * 4 + STM32_BSEC_OTP_OFFSET,
510 sprintf(serial_string, "%08X%08X%08X", otp[0], otp[1], otp[2]);
511 env_set("serial#", serial_string);
516 int arch_misc_init(void)
520 setup_serial_number();