1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
9 #include <asm/arch/system_manager.h>
11 DECLARE_GLOBAL_DATA_PTR;
14 * Configure all the pin muxes
16 void sysmgr_pinmux_init(void)
18 populate_sysmgr_pinmux();
19 populate_sysmgr_fpgaintf_module();
23 * Populate the value for SYSMGR.FPGAINTF.MODULE based on pinmux setting.
24 * The value is not wrote to SYSMGR.FPGAINTF.MODULE but
25 * CONFIG_SYSMGR_ISWGRP_HANDOFF.
27 void populate_sysmgr_fpgaintf_module(void)
31 /* Enable the signal for those HPS peripherals that use FPGA. */
32 if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_NAND_USEFPGA) ==
33 SYSMGR_FPGAINTF_USEFPGA)
34 handoff_val |= SYSMGR_FPGAINTF_NAND;
35 if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_SDMMC_USEFPGA) ==
36 SYSMGR_FPGAINTF_USEFPGA)
37 handoff_val |= SYSMGR_FPGAINTF_SDMMC;
38 if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_SPIM0_USEFPGA) ==
39 SYSMGR_FPGAINTF_USEFPGA)
40 handoff_val |= SYSMGR_FPGAINTF_SPIM0;
41 if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_SPIM1_USEFPGA) ==
42 SYSMGR_FPGAINTF_USEFPGA)
43 handoff_val |= SYSMGR_FPGAINTF_SPIM1;
45 socfpga_get_sysmgr_addr() + SYSMGR_S10_FPGAINTF_EN2);
48 if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_EMAC0_USEFPGA) ==
49 SYSMGR_FPGAINTF_USEFPGA)
50 handoff_val |= SYSMGR_FPGAINTF_EMAC0;
51 if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_EMAC1_USEFPGA) ==
52 SYSMGR_FPGAINTF_USEFPGA)
53 handoff_val |= SYSMGR_FPGAINTF_EMAC1;
54 if (readl(socfpga_get_sysmgr_addr() + SYSMGR_S10_EMAC2_USEFPGA) ==
55 SYSMGR_FPGAINTF_USEFPGA)
56 handoff_val |= SYSMGR_FPGAINTF_EMAC2;
58 socfpga_get_sysmgr_addr() + SYSMGR_S10_FPGAINTF_EN3);
62 * Configure all the pin muxes
64 void populate_sysmgr_pinmux(void)
66 const u32 *sys_mgr_table_u32;
69 /* setup the pin sel */
70 sysmgr_pinmux_table_sel(&sys_mgr_table_u32, &len);
71 for (i = 0; i < len; i = i + 2) {
72 writel(sys_mgr_table_u32[i + 1],
73 sys_mgr_table_u32[i] +
74 (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_S10_PINSEL0);
77 /* setup the pin ctrl */
78 sysmgr_pinmux_table_ctrl(&sys_mgr_table_u32, &len);
79 for (i = 0; i < len; i = i + 2) {
80 writel(sys_mgr_table_u32[i + 1],
81 sys_mgr_table_u32[i] +
82 (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_S10_IOCTRL0);
85 /* setup the fpga use */
86 sysmgr_pinmux_table_fpga(&sys_mgr_table_u32, &len);
87 for (i = 0; i < len; i = i + 2) {
88 writel(sys_mgr_table_u32[i + 1],
89 sys_mgr_table_u32[i] +
90 (u8 *)socfpga_get_sysmgr_addr() +
91 SYSMGR_S10_EMAC0_USEFPGA);
94 /* setup the IO delay */
95 sysmgr_pinmux_table_delay(&sys_mgr_table_u32, &len);
96 for (i = 0; i < len; i = i + 2) {
97 writel(sys_mgr_table_u32[i + 1],
98 sys_mgr_table_u32[i] +
99 (u8 *)socfpga_get_sysmgr_addr() + SYSMGR_S10_IODELAY0);