arch/arm/mach-socfpga/spl_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <asm/io.h>
   8 #include <asm/u-boot.h>
   9 #include <asm/utils.h>
  10 #include <common.h>
  11 #include <debug_uart.h>
  12 #include <image.h>
  13 #include <spl.h>
  14 #include <asm/arch/clock_manager.h>
  15 #include <asm/arch/firewall.h>
  16 #include <asm/arch/mailbox_s10.h>
  17 #include <asm/arch/misc.h>
  18 #include <asm/arch/reset_manager.h>
  19 #include <asm/arch/system_manager.h>
  20 #include <watchdog.h>
  21 #include <dm/uclass.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 u32 spl_boot_device(void)
  26 {
  27         /* TODO: Get from SDM or handoff */
  28         return BOOT_DEVICE_MMC1;
  29 }
  30
  31 #ifdef CONFIG_SPL_MMC_SUPPORT
  32 u32 spl_boot_mode(const u32 boot_device)
  33 {
  34 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  35         return MMCSD_MODE_FS;
  36 #else
  37         return MMCSD_MODE_RAW;
  38 #endif
  39 }
  40 #endif
  41
  42 void board_init_f(ulong dummy)
  43 {
  44         const struct cm_config *cm_default_cfg = cm_get_default_config();
  45         int ret;
  46
  47         ret = spl_early_init();
  48         if (ret)
  49                 hang();
  50
  51         socfpga_get_managers_addr();
  52
  53 #ifdef CONFIG_HW_WATCHDOG
  54         /* Ensure watchdog is paused when debugging is happening */
  55         writel(SYSMGR_WDDBG_PAUSE_ALL_CPU,
  56                socfpga_get_sysmgr_addr() + SYSMGR_SOC64_WDDBG);
  57
  58         /* Enable watchdog before initializing the HW */
  59         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
  60         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
  61         hw_watchdog_init();
  62 #endif
  63
  64         /* ensure all processors are not released prior Linux boot */
  65         writeq(0, CPU_RELEASE_ADDR);
  66
  67         socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
  68         timer_init();
  69
  70         sysmgr_pinmux_init();
  71
  72         /* configuring the HPS clocks */
  73         cm_basic_init(cm_default_cfg);
  74
  75 #ifdef CONFIG_DEBUG_UART
  76         socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
  77         debug_uart_init();
  78 #endif
  79
  80         preloader_console_init();
  81         cm_print_clock_quick_summary();
  82
  83         firewall_setup();
  84
  85         /* disable ocram security at CCU for non secure access */
  86         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
  87                      CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
  88         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
  89                      CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
  90
  91 #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
  92                 struct udevice *dev;
  93
  94                 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
  95                 if (ret) {
  96                         debug("DRAM init failed: %d\n", ret);
  97                         hang();
  98                 }
  99 #endif
 100
 101         mbox_init();
 102
 103 #ifdef CONFIG_CADENCE_QSPI
 104         mbox_qspi_open();
 105 #endif
 106 }