arch/arm/mach-socfpga/spl_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <asm/io.h>
   8 #include <asm/u-boot.h>
   9 #include <asm/utils.h>
  10 #include <common.h>
  11 #include <debug_uart.h>
  12 #include <image.h>
  13 #include <spl.h>
  14 #include <asm/arch/clock_manager.h>
  15 #include <asm/arch/firewall_s10.h>
  16 #include <asm/arch/mailbox_s10.h>
  17 #include <asm/arch/misc.h>
  18 #include <asm/arch/reset_manager.h>
  19 #include <asm/arch/system_manager.h>
  20 #include <watchdog.h>
  21 #include <dm/uclass.h>
  22
  23 DECLARE_GLOBAL_DATA_PTR;
  24
  25 static struct socfpga_system_manager *sysmgr_regs =
  26         (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
  27
  28 u32 spl_boot_device(void)
  29 {
  30         /* TODO: Get from SDM or handoff */
  31         return BOOT_DEVICE_MMC1;
  32 }
  33
  34 #ifdef CONFIG_SPL_MMC_SUPPORT
  35 u32 spl_boot_mode(const u32 boot_device)
  36 {
  37 #if defined(CONFIG_SPL_FS_FAT) || defined(CONFIG_SPL_FS_EXT4)
  38         return MMCSD_MODE_FS;
  39 #else
  40         return MMCSD_MODE_RAW;
  41 #endif
  42 }
  43 #endif
  44
  45 void spl_disable_firewall_l4_per(void)
  46 {
  47         const struct socfpga_firwall_l4_per *firwall_l4_per_base =
  48                 (struct socfpga_firwall_l4_per *)SOCFPGA_FIREWALL_L4_PER;
  49         u32 i;
  50         const u32 *addr[] = {
  51                         &firwall_l4_per_base->nand,
  52                         &firwall_l4_per_base->nand_data,
  53                         &firwall_l4_per_base->usb0,
  54                         &firwall_l4_per_base->usb1,
  55                         &firwall_l4_per_base->spim0,
  56                         &firwall_l4_per_base->spim1,
  57                         &firwall_l4_per_base->emac0,
  58                         &firwall_l4_per_base->emac1,
  59                         &firwall_l4_per_base->emac2,
  60                         &firwall_l4_per_base->sdmmc,
  61                         &firwall_l4_per_base->gpio0,
  62                         &firwall_l4_per_base->gpio1,
  63                         &firwall_l4_per_base->i2c0,
  64                         &firwall_l4_per_base->i2c1,
  65                         &firwall_l4_per_base->i2c2,
  66                         &firwall_l4_per_base->i2c3,
  67                         &firwall_l4_per_base->i2c4,
  68                         &firwall_l4_per_base->timer0,
  69                         &firwall_l4_per_base->timer1,
  70                         &firwall_l4_per_base->uart0,
  71                         &firwall_l4_per_base->uart1
  72                         };
  73
  74         /*
  75          * The following lines of code will enable non-secure access
  76          * to nand, usb, spi, emac, sdmmc, gpio, i2c, timers and uart. This
  77          * is needed as most OS run in non-secure mode. Thus we need to
  78          * enable non-secure access to these peripherals in order for the
  79          * OS to use these peripherals.
  80          */
  81         for (i = 0; i < ARRAY_SIZE(addr); i++)
  82                 writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
  83 }
  84
  85 void spl_disable_firewall_l4_sys(void)
  86 {
  87         const struct socfpga_firwall_l4_sys *firwall_l4_sys_base =
  88                 (struct socfpga_firwall_l4_sys *)SOCFPGA_FIREWALL_L4_SYS;
  89         u32 i;
  90         const u32 *addr[] = {
  91                         &firwall_l4_sys_base->dma_ecc,
  92                         &firwall_l4_sys_base->emac0rx_ecc,
  93                         &firwall_l4_sys_base->emac0tx_ecc,
  94                         &firwall_l4_sys_base->emac1rx_ecc,
  95                         &firwall_l4_sys_base->emac1tx_ecc,
  96                         &firwall_l4_sys_base->emac2rx_ecc,
  97                         &firwall_l4_sys_base->emac2tx_ecc,
  98                         &firwall_l4_sys_base->nand_ecc,
  99                         &firwall_l4_sys_base->nand_read_ecc,
 100                         &firwall_l4_sys_base->nand_write_ecc,
 101                         &firwall_l4_sys_base->ocram_ecc,
 102                         &firwall_l4_sys_base->sdmmc_ecc,
 103                         &firwall_l4_sys_base->usb0_ecc,
 104                         &firwall_l4_sys_base->usb1_ecc,
 105                         &firwall_l4_sys_base->clock_manager,
 106                         &firwall_l4_sys_base->io_manager,
 107                         &firwall_l4_sys_base->reset_manager,
 108                         &firwall_l4_sys_base->system_manager,
 109                         &firwall_l4_sys_base->watchdog0,
 110                         &firwall_l4_sys_base->watchdog1,
 111                         &firwall_l4_sys_base->watchdog2,
 112                         &firwall_l4_sys_base->watchdog3
 113                 };
 114
 115         for (i = 0; i < ARRAY_SIZE(addr); i++)
 116                 writel(FIREWALL_L4_DISABLE_ALL, addr[i]);
 117 }
 118
 119 void board_init_f(ulong dummy)
 120 {
 121         const struct cm_config *cm_default_cfg = cm_get_default_config();
 122         int ret;
 123
 124         ret = spl_early_init();
 125         if (ret)
 126                 hang();
 127
 128         socfpga_get_managers_addr();
 129
 130 #ifdef CONFIG_HW_WATCHDOG
 131         /* Ensure watchdog is paused when debugging is happening */
 132         writel(SYSMGR_WDDBG_PAUSE_ALL_CPU, &sysmgr_regs->wddbg);
 133
 134         /* Enable watchdog before initializing the HW */
 135         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 1);
 136         socfpga_per_reset(SOCFPGA_RESET(L4WD0), 0);
 137         hw_watchdog_init();
 138 #endif
 139
 140         /* ensure all processors are not released prior Linux boot */
 141         writeq(0, CPU_RELEASE_ADDR);
 142
 143         socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
 144         timer_init();
 145
 146         sysmgr_pinmux_init();
 147
 148         /* configuring the HPS clocks */
 149         cm_basic_init(cm_default_cfg);
 150
 151 #ifdef CONFIG_DEBUG_UART
 152         socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
 153         debug_uart_init();
 154 #endif
 155
 156         preloader_console_init();
 157         cm_print_clock_quick_summary();
 158
 159         /* enable non-secure interface to DMA330 DMA and peripherals */
 160         writel(SYSMGR_DMA_IRQ_NS | SYSMGR_DMA_MGR_NS, &sysmgr_regs->dma);
 161         writel(SYSMGR_DMAPERIPH_ALL_NS, &sysmgr_regs->dma_periph);
 162
 163         spl_disable_firewall_l4_per();
 164
 165         spl_disable_firewall_l4_sys();
 166
 167         /* disable lwsocf2fpga and soc2fpga bridge security */
 168         writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_SOC2FPGA);
 169         writel(FIREWALL_BRIDGE_DISABLE_ALL, SOCFPGA_FIREWALL_LWSOC2FPGA);
 170
 171         /* disable SMMU security */
 172         writel(FIREWALL_L4_DISABLE_ALL, SOCFPGA_FIREWALL_TCU);
 173
 174         /* disable ocram security at CCU for non secure access */
 175         clrbits_le32(CCU_REG_ADDR(CCU_CPU0_MPRT_ADMASK_MEM_RAM0),
 176                      CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
 177         clrbits_le32(CCU_REG_ADDR(CCU_IOM_MPRT_ADMASK_MEM_RAM0),
 178                      CCU_ADMASK_P_MASK | CCU_ADMASK_NS_MASK);
 179
 180 #if CONFIG_IS_ENABLED(ALTERA_SDRAM)
 181                 struct udevice *dev;
 182
 183                 ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 184                 if (ret) {
 185                         debug("DRAM init failed: %d\n", ret);
 186                         hang();
 187                 }
 188 #endif
 189
 190         mbox_init();
 191
 192 #ifdef CONFIG_CADENCE_QSPI
 193         mbox_qspi_open();
 194 #endif
 195 }