2 * Copyright (C) 2012 Altera Corporation <www.altera.com>
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/u-boot.h>
11 #include <asm/utils.h>
13 #include <asm/arch/reset_manager.h>
15 #include <asm/arch/system_manager.h>
16 #include <asm/arch/freeze_controller.h>
17 #include <asm/arch/clock_manager.h>
18 #include <asm/arch/scan_manager.h>
19 #include <asm/arch/sdram.h>
20 #include <asm/arch/scu.h>
21 #include <asm/arch/nic301.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 static struct pl310_regs *const pl310 =
26 (struct pl310_regs *)CONFIG_SYS_PL310_BASE;
27 static struct scu_registers *scu_regs =
28 (struct scu_registers *)SOCFPGA_MPUSCU_ADDRESS;
29 static struct nic301_registers *nic301_regs =
30 (struct nic301_registers *)SOCFPGA_L3REGS_ADDRESS;
32 u32 spl_boot_device(void)
34 #ifdef CONFIG_SPL_SPI_SUPPORT
35 socfpga_per_reset(SOCFPGA_RESET(QSPI), 0);
36 return BOOT_DEVICE_SPI;
37 #elif CONFIG_SPL_MMC_SUPPORT
38 socfpga_per_reset(SOCFPGA_RESET(SDMMC), 0);
39 socfpga_per_reset(SOCFPGA_RESET(DMA), 0);
40 return BOOT_DEVICE_MMC1;
42 return BOOT_DEVICE_RAM;
46 #ifdef CONFIG_SPL_MMC_SUPPORT
47 u32 spl_boot_mode(void)
49 #if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
52 return MMCSD_MODE_RAW;
57 static void socfpga_nic301_slave_ns(void)
59 writel(0x1, &nic301_regs->lwhps2fpgaregs);
60 writel(0x1, &nic301_regs->hps2fpgaregs);
61 writel(0x1, &nic301_regs->acp);
62 writel(0x1, &nic301_regs->rom);
63 writel(0x1, &nic301_regs->ocram);
64 writel(0x1, &nic301_regs->sdrdata);
67 void board_init_f(ulong dummy)
69 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
70 const struct cm_config *cm_default_cfg = cm_get_default_config();
72 struct socfpga_system_manager *sysmgr_regs =
73 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
74 unsigned long sdram_size;
78 * First C code to run. Clear fake OCRAM ECC first as SBE
79 * and DBE might triggered during power on
81 reg = readl(&sysmgr_regs->eccgrp_ocram);
82 if (reg & SYSMGR_ECC_OCRAM_SERR)
83 writel(SYSMGR_ECC_OCRAM_SERR | SYSMGR_ECC_OCRAM_EN,
84 &sysmgr_regs->eccgrp_ocram);
85 if (reg & SYSMGR_ECC_OCRAM_DERR)
86 writel(SYSMGR_ECC_OCRAM_DERR | SYSMGR_ECC_OCRAM_EN,
87 &sysmgr_regs->eccgrp_ocram);
89 memset(__bss_start, 0, __bss_end - __bss_start);
91 socfpga_nic301_slave_ns();
93 /* Configure ARM MPU SNSAC register. */
94 setbits_le32(&scu_regs->sacr, 0xfff);
96 /* Remap SDRAM to 0x0 */
97 writel(0x1, &nic301_regs->remap); /* remap.mpuzero */
98 writel(0x1, &pl310->pl310_addr_filter_start);
100 #ifndef CONFIG_SOCFPGA_VIRTUAL_TARGET
101 debug("Freezing all I/O banks\n");
102 /* freeze all IO banks */
103 sys_mgr_frzctrl_freeze_req();
105 /* Put everything into reset but L4WD0. */
106 socfpga_per_reset_all();
107 /* Put FPGA bridges into reset too. */
108 socfpga_bridges_reset(1);
110 socfpga_per_reset(SOCFPGA_RESET(SDR), 0);
111 socfpga_per_reset(SOCFPGA_RESET(UART0), 0);
112 socfpga_per_reset(SOCFPGA_RESET(OSC1TIMER0), 0);
116 debug("Reconfigure Clock Manager\n");
117 /* reconfigure the PLLs */
118 cm_basic_init(cm_default_cfg);
120 /* Enable bootrom to configure IOs. */
121 sysmgr_config_warmrstcfgio(1);
123 /* configure the IOCSR / IO buffer settings */
124 if (scan_mgr_configure_iocsr())
127 sysmgr_config_warmrstcfgio(0);
129 /* configure the pin muxing through system manager */
130 sysmgr_config_warmrstcfgio(1);
131 sysmgr_pinmux_init();
132 sysmgr_config_warmrstcfgio(0);
134 #endif /* CONFIG_SOCFPGA_VIRTUAL_TARGET */
136 /* De-assert reset for peripherals and bridges based on handoff */
137 reset_deassert_peripherals_handoff();
138 socfpga_bridges_reset(0);
140 debug("Unfreezing/Thaw all I/O banks\n");
141 /* unfreeze / thaw all IO banks */
142 sys_mgr_frzctrl_thaw_req();
144 /* enable console uart printing */
145 preloader_console_init();
147 if (sdram_mmr_init_full(0xffffffff) != 0) {
148 puts("SDRAM init failed.\n");
152 debug("SDRAM: Calibrating PHY\n");
153 /* SDRAM calibration */
154 if (sdram_calibration_full() == 0) {
155 puts("SDRAM calibration failed.\n");
159 sdram_size = sdram_calculate_size();
160 debug("SDRAM: %ld MiB\n", sdram_size >> 20);
162 /* Sanity check ensure correct SDRAM size specified */
163 if (get_ram_size(0, sdram_size) != sdram_size) {
164 puts("SDRAM size check failed!\n");
168 socfpga_bridges_reset(1);
170 board_init_r(NULL, 0);