arch/arm/mach-socfpga/reset_manager_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/reset_manager.h>
  10 #include <asm/arch/system_manager.h>
  11 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
  12
  13 DECLARE_GLOBAL_DATA_PTR;
  14
  15 /* Assert or de-assert SoCFPGA reset manager reset. */
  16 void socfpga_per_reset(u32 reset, int set)
  17 {
  18         unsigned long reg;
  19
  20         if (RSTMGR_BANK(reset) == 0)
  21                 reg = RSTMGR_SOC64_MPUMODRST;
  22         else if (RSTMGR_BANK(reset) == 1)
  23                 reg = RSTMGR_SOC64_PER0MODRST;
  24         else if (RSTMGR_BANK(reset) == 2)
  25                 reg = RSTMGR_SOC64_PER1MODRST;
  26         else if (RSTMGR_BANK(reset) == 3)
  27                 reg = RSTMGR_SOC64_BRGMODRST;
  28         else    /* Invalid reset register, do nothing */
  29                 return;
  30
  31         if (set)
  32                 setbits_le32(socfpga_get_rstmgr_addr() + reg,
  33                              1 << RSTMGR_RESET(reset));
  34         else
  35                 clrbits_le32(socfpga_get_rstmgr_addr() + reg,
  36                              1 << RSTMGR_RESET(reset));
  37 }
  38
  39 /*
  40  * Assert reset on every peripheral but L4WD0.
  41  * Watchdog must be kept intact to prevent glitches
  42  * and/or hangs.
  43  */
  44 void socfpga_per_reset_all(void)
  45 {
  46         const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
  47
  48         /* disable all except OCP and l4wd0. OCP disable later */
  49         writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
  50                       socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
  51         writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER0MODRST);
  52         writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_SOC64_PER1MODRST);
  53 }
  54
  55 void socfpga_bridges_reset(int enable)
  56 {
  57         if (enable) {
  58                 /* clear idle request to all bridges */
  59                 setbits_le32(socfpga_get_sysmgr_addr() +
  60                              SYSMGR_SOC64_NOC_IDLEREQ_CLR, ~0);
  61
  62                 /* Release all bridges from reset state */
  63                 clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
  64                              ~0);
  65
  66                 /* Poll until all idleack to 0 */
  67                 while (readl(socfpga_get_sysmgr_addr() +
  68                              SYSMGR_SOC64_NOC_IDLEACK))
  69                         ;
  70         } else {
  71                 /* set idle request to all bridges */
  72                 writel(~0,
  73                        socfpga_get_sysmgr_addr() +
  74                        SYSMGR_SOC64_NOC_IDLEREQ_SET);
  75
  76                 /* Enable the NOC timeout */
  77                 writel(1, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
  78
  79                 /* Poll until all idleack to 1 */
  80                 while ((readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_IDLEACK) ^
  81                         (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
  82                         ;
  83
  84                 /* Poll until all idlestatus to 1 */
  85                 while ((readl(socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_IDLESTATUS) ^
  86                         (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
  87                         ;
  88
  89                 /* Reset all bridges (except NOR DDR scheduler & F2S) */
  90                 setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_BRGMODRST,
  91                              ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
  92                                RSTMGR_BRGMODRST_FPGA2SOC_MASK));
  93
  94                 /* Disable NOC timeout */
  95                 writel(0, socfpga_get_sysmgr_addr() + SYSMGR_SOC64_NOC_TIMEOUT);
  96         }
  97 }
  98
  99 /*
 100  * Return non-zero if the CPU has been warm reset
 101  */
 102 int cpu_has_been_warmreset(void)
 103 {
 104         return readl(socfpga_get_rstmgr_addr() + RSTMGR_SOC64_STATUS) &
 105                         RSTMGR_L4WD_MPU_WARMRESET_MASK;
 106 }