arch/arm/mach-socfpga/reset_manager_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/reset_manager.h>
  10 #include <asm/arch/system_manager.h>
  11 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
  12
  13 DECLARE_GLOBAL_DATA_PTR;
  14
  15 static const struct socfpga_system_manager *system_manager_base =
  16                 (void *)SOCFPGA_SYSMGR_ADDRESS;
  17
  18 /* Assert or de-assert SoCFPGA reset manager reset. */
  19 void socfpga_per_reset(u32 reset, int set)
  20 {
  21         unsigned long reg;
  22
  23         if (RSTMGR_BANK(reset) == 0)
  24                 reg = RSTMGR_S10_MPUMODRST;
  25         else if (RSTMGR_BANK(reset) == 1)
  26                 reg = RSTMGR_S10_PER0MODRST;
  27         else if (RSTMGR_BANK(reset) == 2)
  28                 reg = RSTMGR_S10_PER1MODRST;
  29         else if (RSTMGR_BANK(reset) == 3)
  30                 reg = RSTMGR_S10_BRGMODRST;
  31         else    /* Invalid reset register, do nothing */
  32                 return;
  33
  34         if (set)
  35                 setbits_le32(socfpga_get_rstmgr_addr() + reg,
  36                              1 << RSTMGR_RESET(reset));
  37         else
  38                 clrbits_le32(socfpga_get_rstmgr_addr() + reg,
  39                              1 << RSTMGR_RESET(reset));
  40 }
  41
  42 /*
  43  * Assert reset on every peripheral but L4WD0.
  44  * Watchdog must be kept intact to prevent glitches
  45  * and/or hangs.
  46  */
  47 void socfpga_per_reset_all(void)
  48 {
  49         const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
  50
  51         /* disable all except OCP and l4wd0. OCP disable later */
  52         writel(~(l4wd0 | RSTMGR_PER0MODRST_OCP_MASK),
  53                       socfpga_get_rstmgr_addr() + RSTMGR_S10_PER0MODRST);
  54         writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_S10_PER0MODRST);
  55         writel(0xffffffff, socfpga_get_rstmgr_addr() + RSTMGR_S10_PER1MODRST);
  56 }
  57
  58 void socfpga_bridges_reset(int enable)
  59 {
  60         if (enable) {
  61                 /* clear idle request to all bridges */
  62                 setbits_le32(&system_manager_base->noc_idlereq_clr, ~0);
  63
  64                 /* Release all bridges from reset state */
  65                 clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_S10_BRGMODRST,
  66                              ~0);
  67
  68                 /* Poll until all idleack to 0 */
  69                 while (readl(&system_manager_base->noc_idleack))
  70                         ;
  71         } else {
  72                 /* set idle request to all bridges */
  73                 writel(~0, &system_manager_base->noc_idlereq_set);
  74
  75                 /* Enable the NOC timeout */
  76                 writel(1, &system_manager_base->noc_timeout);
  77
  78                 /* Poll until all idleack to 1 */
  79                 while ((readl(&system_manager_base->noc_idleack) ^
  80                         (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
  81                         ;
  82
  83                 /* Poll until all idlestatus to 1 */
  84                 while ((readl(&system_manager_base->noc_idlestatus) ^
  85                         (SYSMGR_NOC_H2F_MSK | SYSMGR_NOC_LWH2F_MSK)))
  86                         ;
  87
  88                 /* Reset all bridges (except NOR DDR scheduler & F2S) */
  89                 setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_S10_BRGMODRST,
  90                              ~(RSTMGR_BRGMODRST_DDRSCH_MASK |
  91                                RSTMGR_BRGMODRST_FPGA2SOC_MASK));
  92
  93                 /* Disable NOC timeout */
  94                 writel(0, &system_manager_base->noc_timeout);
  95         }
  96 }
  97
  98 /*
  99  * Return non-zero if the CPU has been warm reset
 100  */
 101 int cpu_has_been_warmreset(void)
 102 {
 103         return readl(socfpga_get_rstmgr_addr() + RSTMGR_S10_STATUS) &
 104                         RSTMGR_L4WD_MPU_WARMRESET_MASK;
 105 }