1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2013 Altera Corporation <www.altera.com>
9 #include <asm/arch/fpga_manager.h>
10 #include <asm/arch/reset_manager.h>
11 #include <asm/arch/system_manager.h>
13 static const struct socfpga_reset_manager *reset_manager_base =
14 (void *)SOCFPGA_RSTMGR_ADDRESS;
15 static const struct socfpga_system_manager *sysmgr_regs =
16 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
18 /* Assert or de-assert SoCFPGA reset manager reset. */
19 void socfpga_per_reset(u32 reset, int set)
22 u32 rstmgr_bank = RSTMGR_BANK(reset);
24 switch (rstmgr_bank) {
26 reg = &reset_manager_base->mpu_mod_reset;
29 reg = &reset_manager_base->per_mod_reset;
32 reg = &reset_manager_base->per2_mod_reset;
35 reg = &reset_manager_base->brg_mod_reset;
38 reg = &reset_manager_base->misc_mod_reset;
46 setbits_le32(reg, 1 << RSTMGR_RESET(reset));
48 clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
52 * Assert reset on every peripheral but L4WD0.
53 * Watchdog must be kept intact to prevent glitches
56 void socfpga_per_reset_all(void)
58 const u32 l4wd0 = 1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0));
60 writel(~l4wd0, &reset_manager_base->per_mod_reset);
61 writel(0xffffffff, &reset_manager_base->per2_mod_reset);
65 * Release peripherals from reset based on handoff
67 void reset_deassert_peripherals_handoff(void)
69 writel(0, &reset_manager_base->per_mod_reset);
72 #define L3REGS_REMAP_LWHPS2FPGA_MASK 0x10
73 #define L3REGS_REMAP_HPS2FPGA_MASK 0x08
74 #define L3REGS_REMAP_OCRAM_MASK 0x01
76 void socfpga_bridges_set_handoff_regs(bool h2f, bool lwh2f, bool f2h)
79 u32 l3rmask = L3REGS_REMAP_OCRAM_MASK;
84 l3rmask |= L3REGS_REMAP_HPS2FPGA_MASK;
89 l3rmask |= L3REGS_REMAP_LWHPS2FPGA_MASK;
94 writel(brgmask, &sysmgr_regs->iswgrp_handoff[0]);
95 writel(l3rmask, &sysmgr_regs->iswgrp_handoff[1]);
98 void socfpga_bridges_reset(int enable)
100 const u32 l3mask = L3REGS_REMAP_LWHPS2FPGA_MASK |
101 L3REGS_REMAP_HPS2FPGA_MASK |
102 L3REGS_REMAP_OCRAM_MASK;
106 writel(0x7, &reset_manager_base->brg_mod_reset);
107 writel(L3REGS_REMAP_OCRAM_MASK, SOCFPGA_L3REGS_ADDRESS);
109 socfpga_bridges_set_handoff_regs(false, false, false);
111 /* Check signal from FPGA. */
112 if (!fpgamgr_test_fpga_ready()) {
113 /* FPGA not ready, do nothing. We allow system to boot
114 * without FPGA ready. So, return 0 instead of error. */
115 printf("%s: FPGA not ready, aborting.\n", __func__);
120 writel(0, &reset_manager_base->brg_mod_reset);
122 /* Remap the bridges into memory map */
123 writel(l3mask, SOCFPGA_L3REGS_ADDRESS);