1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2017 Intel Corporation
7 #include <asm/arch/fpga_manager.h>
8 #include <asm/arch/misc.h>
9 #include <asm/arch/reset_manager.h>
10 #include <asm/arch/system_manager.h>
16 DECLARE_GLOBAL_DATA_PTR;
18 static const struct socfpga_reset_manager *reset_manager_base =
19 (void *)SOCFPGA_RSTMGR_ADDRESS;
20 static const struct socfpga_system_manager *sysmgr_regs =
21 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
29 static const struct bridge_cfg bridge_cfg_tbl[] = {
31 COMPAT_ALTERA_SOCFPGA_H2F_BRG,
32 ALT_SYSMGR_NOC_H2F_SET_MSK,
33 ALT_RSTMGR_BRGMODRST_H2F_SET_MSK,
36 COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,
37 ALT_SYSMGR_NOC_LWH2F_SET_MSK,
38 ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK,
41 COMPAT_ALTERA_SOCFPGA_F2H_BRG,
42 ALT_SYSMGR_NOC_F2H_SET_MSK,
43 ALT_RSTMGR_BRGMODRST_F2H_SET_MSK,
46 COMPAT_ALTERA_SOCFPGA_F2SDR0,
47 ALT_SYSMGR_NOC_F2SDR0_SET_MSK,
48 ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK,
51 COMPAT_ALTERA_SOCFPGA_F2SDR1,
52 ALT_SYSMGR_NOC_F2SDR1_SET_MSK,
53 ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK,
56 COMPAT_ALTERA_SOCFPGA_F2SDR2,
57 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
58 ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK,
62 /* Disable the watchdog (toggle reset to watchdog) */
63 void socfpga_watchdog_disable(void)
65 /* assert reset for watchdog */
66 setbits_le32(&reset_manager_base->per1modrst,
67 ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
70 /* Release NOC ddr scheduler from reset */
71 void socfpga_reset_deassert_noc_ddr_scheduler(void)
73 clrbits_le32(&reset_manager_base->brgmodrst,
74 ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
77 static int get_bridge_init_val(const void *blob, int compat_id)
81 node = fdtdec_next_compatible(blob, 0, compat_id);
85 return fdtdec_get_uint(blob, node, "init-val", 0);
88 /* Enable bridges (hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram) per handoff */
89 int socfpga_reset_deassert_bridges_handoff(void)
91 u32 mask_noc = 0, mask_rstmgr = 0;
94 for (i = 0; i < ARRAY_SIZE(bridge_cfg_tbl); i++) {
95 if (get_bridge_init_val(gd->fdt_blob,
96 bridge_cfg_tbl[i].compat_id)) {
97 mask_noc |= bridge_cfg_tbl[i].mask_noc;
98 mask_rstmgr |= bridge_cfg_tbl[i].mask_rstmgr;
102 /* clear idle request to all bridges */
103 setbits_le32(&sysmgr_regs->noc_idlereq_clr, mask_noc);
105 /* Release bridges from reset state per handoff value */
106 clrbits_le32(&reset_manager_base->brgmodrst, mask_rstmgr);
108 /* Poll until all idleack to 0, timeout at 1000ms */
109 return wait_for_bit_le32(&sysmgr_regs->noc_idleack, mask_noc,
113 /* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
114 void socfpga_reset_deassert_osc1wd0(void)
116 clrbits_le32(&reset_manager_base->per1modrst,
117 ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
121 * Assert or de-assert SoCFPGA reset manager reset.
123 void socfpga_per_reset(u32 reset, int set)
126 u32 rstmgr_bank = RSTMGR_BANK(reset);
128 switch (rstmgr_bank) {
130 reg = &reset_manager_base->mpumodrst;
133 reg = &reset_manager_base->per0modrst;
136 reg = &reset_manager_base->per1modrst;
139 reg = &reset_manager_base->brgmodrst;
142 reg = &reset_manager_base->sysmodrst;
150 setbits_le32(reg, 1 << RSTMGR_RESET(reset));
152 clrbits_le32(reg, 1 << RSTMGR_RESET(reset));
156 * Assert reset on every peripheral but L4WD0.
157 * Watchdog must be kept intact to prevent glitches
159 * For the Arria10, we disable all the peripherals except L4 watchdog0,
160 * L4 Timer 0, and ECC.
162 void socfpga_per_reset_all(void)
164 const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
165 (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
166 unsigned mask_ecc_ocp =
167 ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
168 ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
169 ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
170 ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK |
171 ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK |
172 ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
173 ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
174 ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
176 /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
177 writel(~l4wd0, &reset_manager_base->per1modrst);
178 setbits_le32(&reset_manager_base->per0modrst, ~mask_ecc_ocp);
180 /* Finally disable the ECC_OCP */
181 setbits_le32(&reset_manager_base->per0modrst, mask_ecc_ocp);
184 int socfpga_bridges_reset(void)
188 /* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps,
190 /* set idle request to all bridges */
191 writel(ALT_SYSMGR_NOC_H2F_SET_MSK |
192 ALT_SYSMGR_NOC_LWH2F_SET_MSK |
193 ALT_SYSMGR_NOC_F2H_SET_MSK |
194 ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
195 ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
196 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
197 &sysmgr_regs->noc_idlereq_set);
199 /* Enable the NOC timeout */
200 writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK, &sysmgr_regs->noc_timeout);
202 /* Poll until all idleack to 1 */
203 ret = wait_for_bit_le32(&sysmgr_regs->noc_idleack,
204 ALT_SYSMGR_NOC_H2F_SET_MSK |
205 ALT_SYSMGR_NOC_LWH2F_SET_MSK |
206 ALT_SYSMGR_NOC_F2H_SET_MSK |
207 ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
208 ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
209 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
214 /* Poll until all idlestatus to 1 */
215 ret = wait_for_bit_le32(&sysmgr_regs->noc_idlestatus,
216 ALT_SYSMGR_NOC_H2F_SET_MSK |
217 ALT_SYSMGR_NOC_LWH2F_SET_MSK |
218 ALT_SYSMGR_NOC_F2H_SET_MSK |
219 ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
220 ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
221 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
226 /* Put all bridges (except NOR DDR scheduler) into reset state */
227 setbits_le32(&reset_manager_base->brgmodrst,
228 (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
229 ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
230 ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
231 ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
232 ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
233 ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
235 /* Disable NOC timeout */
236 writel(0, &sysmgr_regs->noc_timeout);