arch/arm/mach-socfpga/reset_manager_arria10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2017 Intel Corporation
   4  */
   5
   6 #include <asm/io.h>
   7 #include <asm/arch/fpga_manager.h>
   8 #include <asm/arch/misc.h>
   9 #include <asm/arch/reset_manager.h>
  10 #include <asm/arch/system_manager.h>
  11 #include <common.h>
  12 #include <errno.h>
  13 #include <fdtdec.h>
  14 #include <wait_bit.h>
  15
  16 DECLARE_GLOBAL_DATA_PTR;
  17
  18 struct bridge_cfg {
  19         int compat_id;
  20         u32  mask_noc;
  21         u32  mask_rstmgr;
  22 };
  23
  24 static const struct bridge_cfg bridge_cfg_tbl[] = {
  25         {
  26                 COMPAT_ALTERA_SOCFPGA_H2F_BRG,
  27                 ALT_SYSMGR_NOC_H2F_SET_MSK,
  28                 ALT_RSTMGR_BRGMODRST_H2F_SET_MSK,
  29         },
  30         {
  31                 COMPAT_ALTERA_SOCFPGA_LWH2F_BRG,
  32                 ALT_SYSMGR_NOC_LWH2F_SET_MSK,
  33                 ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK,
  34         },
  35         {
  36                 COMPAT_ALTERA_SOCFPGA_F2H_BRG,
  37                 ALT_SYSMGR_NOC_F2H_SET_MSK,
  38                 ALT_RSTMGR_BRGMODRST_F2H_SET_MSK,
  39         },
  40         {
  41                 COMPAT_ALTERA_SOCFPGA_F2SDR0,
  42                 ALT_SYSMGR_NOC_F2SDR0_SET_MSK,
  43                 ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK,
  44         },
  45         {
  46                 COMPAT_ALTERA_SOCFPGA_F2SDR1,
  47                 ALT_SYSMGR_NOC_F2SDR1_SET_MSK,
  48                 ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK,
  49         },
  50         {
  51                 COMPAT_ALTERA_SOCFPGA_F2SDR2,
  52                 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
  53                 ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK,
  54         },
  55 };
  56
  57 /* Disable the watchdog (toggle reset to watchdog) */
  58 void socfpga_watchdog_disable(void)
  59 {
  60         /* assert reset for watchdog */
  61         setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST,
  62                      ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
  63 }
  64
  65 /* Release NOC ddr scheduler from reset */
  66 void socfpga_reset_deassert_noc_ddr_scheduler(void)
  67 {
  68         clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
  69                      ALT_RSTMGR_BRGMODRST_DDRSCH_SET_MSK);
  70 }
  71
  72 static int get_bridge_init_val(const void *blob, int compat_id)
  73 {
  74         int node;
  75
  76         node = fdtdec_next_compatible(blob, 0, compat_id);
  77         if (node < 0)
  78                 return 0;
  79
  80         return fdtdec_get_uint(blob, node, "init-val", 0);
  81 }
  82
  83 /* Enable bridges (hps2fpga, lwhps2fpga, fpga2hps, fpga2sdram) per handoff */
  84 int socfpga_reset_deassert_bridges_handoff(void)
  85 {
  86         u32 mask_noc = 0, mask_rstmgr = 0;
  87         int i;
  88
  89         for (i = 0; i < ARRAY_SIZE(bridge_cfg_tbl); i++) {
  90                 if (get_bridge_init_val(gd->fdt_blob,
  91                                         bridge_cfg_tbl[i].compat_id)) {
  92                         mask_noc |= bridge_cfg_tbl[i].mask_noc;
  93                         mask_rstmgr |= bridge_cfg_tbl[i].mask_rstmgr;
  94                 }
  95         }
  96
  97         /* clear idle request to all bridges */
  98         setbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_IDLEREQ_CLR,
  99                      mask_noc);
 100
 101         /* Release bridges from reset state per handoff value */
 102         clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
 103                      mask_rstmgr);
 104
 105         /* Poll until all idleack to 0, timeout at 1000ms */
 106         return wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
 107                                  SYSMGR_A10_NOC_IDLEACK),
 108                                  mask_noc, false, 1000, false);
 109 }
 110
 111 /* Release L4 OSC1 Watchdog Timer 0 from reset through reset manager */
 112 void socfpga_reset_deassert_osc1wd0(void)
 113 {
 114         clrbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST,
 115                      ALT_RSTMGR_PER1MODRST_WD0_SET_MSK);
 116 }
 117
 118 /*
 119  * Assert or de-assert SoCFPGA reset manager reset.
 120  */
 121 void socfpga_per_reset(u32 reset, int set)
 122 {
 123         unsigned long reg;
 124         u32 rstmgr_bank = RSTMGR_BANK(reset);
 125
 126         switch (rstmgr_bank) {
 127         case 0:
 128                 reg = RSTMGR_A10_MPUMODRST;
 129                 break;
 130         case 1:
 131                 reg = RSTMGR_A10_PER0MODRST;
 132                 break;
 133         case 2:
 134                 reg = RSTMGR_A10_PER1MODRST;
 135                 break;
 136         case 3:
 137                 reg = RSTMGR_A10_BRGMODRST;
 138                 break;
 139         case 4:
 140                 reg = RSTMGR_A10_SYSMODRST;
 141                 break;
 142
 143         default:
 144                 return;
 145         }
 146
 147         if (set)
 148                 setbits_le32(socfpga_get_rstmgr_addr() + reg,
 149                              1 << RSTMGR_RESET(reset));
 150         else
 151                 clrbits_le32(socfpga_get_rstmgr_addr() + reg,
 152                              1 << RSTMGR_RESET(reset));
 153 }
 154
 155 /*
 156  * Assert reset on every peripheral but L4WD0.
 157  * Watchdog must be kept intact to prevent glitches
 158  * and/or hangs.
 159  * For the Arria10, we disable all the peripherals except L4 watchdog0,
 160  * L4 Timer 0, and ECC.
 161  */
 162 void socfpga_per_reset_all(void)
 163 {
 164         const u32 l4wd0 = (1 << RSTMGR_RESET(SOCFPGA_RESET(L4WD0)) |
 165                           (1 << RSTMGR_RESET(SOCFPGA_RESET(L4SYSTIMER0))));
 166         unsigned mask_ecc_ocp =
 167                 ALT_RSTMGR_PER0MODRST_EMACECC0_SET_MSK |
 168                 ALT_RSTMGR_PER0MODRST_EMACECC1_SET_MSK |
 169                 ALT_RSTMGR_PER0MODRST_EMACECC2_SET_MSK |
 170                 ALT_RSTMGR_PER0MODRST_USBECC0_SET_MSK |
 171                 ALT_RSTMGR_PER0MODRST_USBECC1_SET_MSK |
 172                 ALT_RSTMGR_PER0MODRST_NANDECC_SET_MSK |
 173                 ALT_RSTMGR_PER0MODRST_QSPIECC_SET_MSK |
 174                 ALT_RSTMGR_PER0MODRST_SDMMCECC_SET_MSK;
 175
 176         /* disable all components except ECC_OCP, L4 Timer0 and L4 WD0 */
 177         writel(~l4wd0, socfpga_get_rstmgr_addr() + RSTMGR_A10_PER1MODRST);
 178         setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST,
 179                      ~mask_ecc_ocp);
 180
 181         /* Finally disable the ECC_OCP */
 182         setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_PER0MODRST,
 183                      mask_ecc_ocp);
 184 }
 185
 186 int socfpga_bridges_reset(void)
 187 {
 188         int ret;
 189
 190         /* Disable all the bridges (hps2fpga, lwhps2fpga, fpga2hps,
 191            fpga2sdram) */
 192         /* set idle request to all bridges */
 193         writel(ALT_SYSMGR_NOC_H2F_SET_MSK |
 194                 ALT_SYSMGR_NOC_LWH2F_SET_MSK |
 195                 ALT_SYSMGR_NOC_F2H_SET_MSK |
 196                 ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
 197                 ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
 198                 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
 199                 socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_IDLEREQ_SET);
 200
 201         /* Enable the NOC timeout */
 202         writel(ALT_SYSMGR_NOC_TMO_EN_SET_MSK,
 203                socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_TIMEOUT);
 204
 205         /* Poll until all idleack to 1 */
 206         ret = wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
 207                                 SYSMGR_A10_NOC_IDLEACK),
 208                                 ALT_SYSMGR_NOC_H2F_SET_MSK |
 209                                 ALT_SYSMGR_NOC_LWH2F_SET_MSK |
 210                                 ALT_SYSMGR_NOC_F2H_SET_MSK |
 211                                 ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
 212                                 ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
 213                                 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
 214                                 true, 10000, false);
 215         if (ret)
 216                 return ret;
 217
 218         /* Poll until all idlestatus to 1 */
 219         ret = wait_for_bit_le32((const void *)(socfpga_get_sysmgr_addr() +
 220                                 SYSMGR_A10_NOC_IDLESTATUS),
 221                                 ALT_SYSMGR_NOC_H2F_SET_MSK |
 222                                 ALT_SYSMGR_NOC_LWH2F_SET_MSK |
 223                                 ALT_SYSMGR_NOC_F2H_SET_MSK |
 224                                 ALT_SYSMGR_NOC_F2SDR0_SET_MSK |
 225                                 ALT_SYSMGR_NOC_F2SDR1_SET_MSK |
 226                                 ALT_SYSMGR_NOC_F2SDR2_SET_MSK,
 227                                 true, 10000, false);
 228         if (ret)
 229                 return ret;
 230
 231         /* Put all bridges (except NOR DDR scheduler) into reset state */
 232         setbits_le32(socfpga_get_rstmgr_addr() + RSTMGR_A10_BRGMODRST,
 233                      (ALT_RSTMGR_BRGMODRST_H2F_SET_MSK |
 234                       ALT_RSTMGR_BRGMODRST_LWH2F_SET_MSK |
 235                       ALT_RSTMGR_BRGMODRST_F2H_SET_MSK |
 236                       ALT_RSTMGR_BRGMODRST_F2SSDRAM0_SET_MSK |
 237                       ALT_RSTMGR_BRGMODRST_F2SSDRAM1_SET_MSK |
 238                       ALT_RSTMGR_BRGMODRST_F2SSDRAM2_SET_MSK));
 239
 240         /* Disable NOC timeout */
 241         writel(0, socfpga_get_sysmgr_addr() + SYSMGR_A10_NOC_TIMEOUT);
 242
 243         return 0;
 244 }