arch/arm/mach-socfpga/mmu-arm64_s10.c

   1 // SPDX-License-Identifier: GPL-2.0
   2 /*
   3  * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
   4  *
   5  */
   6
   7 #include <common.h>
   8 #include <asm/armv8/mmu.h>
   9
  10 DECLARE_GLOBAL_DATA_PTR;
  11
  12 static struct mm_region socfpga_stratix10_mem_map[] = {
  13         {
  14                 /* MEM 2GB*/
  15                 .virt   = 0x0UL,
  16                 .phys   = 0x0UL,
  17                 .size   = 0x80000000UL,
  18                 .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  19                                 PTE_BLOCK_INNER_SHARE,
  20         }, {
  21                 /* FPGA 1.5GB */
  22                 .virt   = 0x80000000UL,
  23                 .phys   = 0x80000000UL,
  24                 .size   = 0x60000000UL,
  25                 .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  26                                 PTE_BLOCK_NON_SHARE |
  27                                 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
  28         }, {
  29                 /* DEVICE 142MB */
  30                 .virt   = 0xF7000000UL,
  31                 .phys   = 0xF7000000UL,
  32                 .size   = 0x08E00000UL,
  33                 .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  34                                 PTE_BLOCK_NON_SHARE |
  35                                 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
  36         }, {
  37                 /* OCRAM 1MB but available 256KB */
  38                 .virt   = 0xFFE00000UL,
  39                 .phys   = 0xFFE00000UL,
  40                 .size   = 0x00100000UL,
  41                 .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  42                                 PTE_BLOCK_INNER_SHARE,
  43         }, {
  44                 /* DEVICE 32KB */
  45                 .virt   = 0xFFFC0000UL,
  46                 .phys   = 0xFFFC0000UL,
  47                 .size   = 0x00008000UL,
  48                 .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  49                                 PTE_BLOCK_NON_SHARE |
  50                                 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
  51         }, {
  52                 /* MEM 124GB */
  53                 .virt   = 0x0100000000UL,
  54                 .phys   = 0x0100000000UL,
  55                 .size   = 0x1F00000000UL,
  56                 .attrs  = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  57                                 PTE_BLOCK_INNER_SHARE,
  58         }, {
  59                 /* DEVICE 4GB */
  60                 .virt   = 0x2000000000UL,
  61                 .phys   = 0x2000000000UL,
  62                 .size   = 0x0100000000UL,
  63                 .attrs  = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  64                                 PTE_BLOCK_NON_SHARE |
  65                                 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
  66         }, {
  67                 /* List terminator */
  68         },
  69 };
  70
  71 struct mm_region *mem_map = socfpga_stratix10_mem_map;