1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
8 #include <asm/armv8/mmu.h>
10 DECLARE_GLOBAL_DATA_PTR;
12 static struct mm_region socfpga_stratix10_mem_map[] = {
18 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
19 PTE_BLOCK_INNER_SHARE,
25 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
27 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
33 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
35 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
37 /* OCRAM 1MB but available 256KB */
41 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
42 PTE_BLOCK_INNER_SHARE,
48 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
50 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
53 .virt = 0x0100000000UL,
54 .phys = 0x0100000000UL,
55 .size = 0x1F00000000UL,
56 .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
57 PTE_BLOCK_INNER_SHARE,
60 .virt = 0x2000000000UL,
61 .phys = 0x2000000000UL,
62 .size = 0x0100000000UL,
63 .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
65 PTE_BLOCK_PXN | PTE_BLOCK_UXN,
71 struct mm_region *mem_map = socfpga_stratix10_mem_map;