1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
14 #include <asm/arch/reset_manager.h>
15 #include <asm/arch/system_manager.h>
16 #include <asm/arch/misc.h>
17 #include <asm/pl310.h>
18 #include <linux/libfdt.h>
19 #include <asm/arch/mailbox_s10.h>
21 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 static struct socfpga_system_manager *sysmgr_regs =
26 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
29 * FPGA programming support for SoC FPGA Stratix 10
31 static Altera_desc altera_fpga[] = {
36 secure_device_manager_mailbox,
37 /* No limitation as additional data will be ignored */
39 /* No device function table */
41 /* Base interface address specified in driver */
43 /* No cookie implementation */
49 * DesignWare Ethernet initialization
51 #ifdef CONFIG_ETH_DESIGNWARE
53 static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
60 if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii") ||
61 !strcmp(phymode, "sgmii"))
62 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
63 else if (!strcmp(phymode, "rgmii"))
64 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
65 else if (!strcmp(phymode, "rmii"))
66 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
70 clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index,
71 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
77 static int socfpga_set_phymode(void)
79 const void *fdt = gd->fdt_blob;
80 struct fdtdec_phandle_args args;
83 int nodes[3]; /* Max. 3 GMACs */
87 count = fdtdec_find_aliases_for_id(fdt, "ethernet",
88 COMPAT_ALTERA_SOCFPGA_DWMAC,
89 nodes, ARRAY_SIZE(nodes));
90 for (i = 0; i < count; i++) {
95 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
98 if (ret || args.args_count != 1) {
99 debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
103 gmac_index = args.args[0] - EMAC0_RESET;
105 phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
106 ret = socfpga_phymode_setup(gmac_index, phy_mode);
108 debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
116 static int socfpga_set_phymode(void)
123 * Print CPU information
125 #if defined(CONFIG_DISPLAY_CPUINFO)
126 int print_cpuinfo(void)
128 puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
134 #ifdef CONFIG_ARCH_MISC_INIT
135 int arch_misc_init(void)
137 char qspi_string[13];
139 sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
140 env_set("qspi_clock", qspi_string);
142 socfpga_set_phymode();
147 int arch_early_init_r(void)
149 socfpga_fpga_add(&altera_fpga[0]);
154 void do_bridge_reset(int enable, unsigned int mask)
156 /* Check FPGA status before bridge enable */
158 int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
160 if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
161 ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
167 socfpga_bridges_reset(enable);