1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
15 #include <asm/arch/reset_manager.h>
16 #include <asm/arch/system_manager.h>
17 #include <asm/arch/misc.h>
18 #include <asm/pl310.h>
19 #include <linux/libfdt.h>
20 #include <asm/arch/mailbox_s10.h>
22 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
24 DECLARE_GLOBAL_DATA_PTR;
27 * FPGA programming support for SoC FPGA Stratix 10
29 static Altera_desc altera_fpga[] = {
34 secure_device_manager_mailbox,
35 /* No limitation as additional data will be ignored */
37 /* No device function table */
39 /* Base interface address specified in driver */
41 /* No cookie implementation */
47 * DesignWare Ethernet initialization
49 #ifdef CONFIG_ETH_DESIGNWARE
51 static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
58 if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii") ||
59 !strcmp(phymode, "sgmii"))
60 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
61 else if (!strcmp(phymode, "rgmii"))
62 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
63 else if (!strcmp(phymode, "rmii"))
64 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
68 clrsetbits_le32(socfpga_get_sysmgr_addr() + SYSMGR_S10_EMAC0 +
70 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK, modereg);
75 static int socfpga_set_phymode(void)
77 const void *fdt = gd->fdt_blob;
78 struct fdtdec_phandle_args args;
81 int nodes[3]; /* Max. 3 GMACs */
85 count = fdtdec_find_aliases_for_id(fdt, "ethernet",
86 COMPAT_ALTERA_SOCFPGA_DWMAC,
87 nodes, ARRAY_SIZE(nodes));
88 for (i = 0; i < count; i++) {
93 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
96 if (ret || args.args_count != 1) {
97 debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
101 gmac_index = args.args[0] - EMAC0_RESET;
103 phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
104 ret = socfpga_phymode_setup(gmac_index, phy_mode);
106 debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
114 static int socfpga_set_phymode(void)
121 * Print CPU information
123 #if defined(CONFIG_DISPLAY_CPUINFO)
124 int print_cpuinfo(void)
126 puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
132 #ifdef CONFIG_ARCH_MISC_INIT
133 int arch_misc_init(void)
135 char qspi_string[13];
137 sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
138 env_set("qspi_clock", qspi_string);
140 socfpga_set_phymode();
145 int arch_early_init_r(void)
147 socfpga_fpga_add(&altera_fpga[0]);
152 void do_bridge_reset(int enable, unsigned int mask)
154 /* Check FPGA status before bridge enable */
156 int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
158 if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
159 ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
165 socfpga_bridges_reset(enable);