1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
14 #include <asm/arch/reset_manager.h>
15 #include <asm/arch/system_manager.h>
16 #include <asm/arch/misc.h>
17 #include <asm/pl310.h>
18 #include <linux/libfdt.h>
20 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 static struct socfpga_system_manager *sysmgr_regs =
25 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
28 * FPGA programming support for SoC FPGA Stratix 10
30 static Altera_desc altera_fpga[] = {
35 secure_device_manager_mailbox,
36 /* No limitation as additional data will be ignored */
38 /* No device function table */
40 /* Base interface address specified in driver */
42 /* No cookie implementation */
48 * DesignWare Ethernet initialization
50 #ifdef CONFIG_ETH_DESIGNWARE
52 static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
59 if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii") ||
60 !strcmp(phymode, "sgmii"))
61 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
62 else if (!strcmp(phymode, "rgmii"))
63 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
64 else if (!strcmp(phymode, "rmii"))
65 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
69 clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index,
70 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
76 static int socfpga_set_phymode(void)
78 const void *fdt = gd->fdt_blob;
79 struct fdtdec_phandle_args args;
82 int nodes[3]; /* Max. 3 GMACs */
86 count = fdtdec_find_aliases_for_id(fdt, "ethernet",
87 COMPAT_ALTERA_SOCFPGA_DWMAC,
88 nodes, ARRAY_SIZE(nodes));
89 for (i = 0; i < count; i++) {
94 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
97 if (ret || args.args_count != 1) {
98 debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
102 gmac_index = args.args[0] - EMAC0_RESET;
104 phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
105 ret = socfpga_phymode_setup(gmac_index, phy_mode);
107 debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
115 static int socfpga_set_phymode(void)
122 * Print CPU information
124 #if defined(CONFIG_DISPLAY_CPUINFO)
125 int print_cpuinfo(void)
127 puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
133 #ifdef CONFIG_ARCH_MISC_INIT
134 int arch_misc_init(void)
136 char qspi_string[13];
138 sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
139 env_set("qspi_clock", qspi_string);
141 socfpga_set_phymode();
146 int arch_early_init_r(void)
148 socfpga_fpga_add(&altera_fpga[0]);
153 void do_bridge_reset(int enable)
155 socfpga_bridges_reset(enable);