1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright (C) 2016-2018 Intel Corporation <www.intel.com>
15 #include <asm/arch/reset_manager.h>
16 #include <asm/arch/system_manager.h>
17 #include <asm/arch/misc.h>
18 #include <asm/pl310.h>
19 #include <linux/libfdt.h>
20 #include <asm/arch/mailbox_s10.h>
22 #include <dt-bindings/reset/altr,rst-mgr-s10.h>
24 DECLARE_GLOBAL_DATA_PTR;
26 static struct socfpga_system_manager *sysmgr_regs =
27 (struct socfpga_system_manager *)SOCFPGA_SYSMGR_ADDRESS;
30 * FPGA programming support for SoC FPGA Stratix 10
32 static Altera_desc altera_fpga[] = {
37 secure_device_manager_mailbox,
38 /* No limitation as additional data will be ignored */
40 /* No device function table */
42 /* Base interface address specified in driver */
44 /* No cookie implementation */
50 * DesignWare Ethernet initialization
52 #ifdef CONFIG_ETH_DESIGNWARE
54 static u32 socfpga_phymode_setup(u32 gmac_index, const char *phymode)
61 if (!strcmp(phymode, "mii") || !strcmp(phymode, "gmii") ||
62 !strcmp(phymode, "sgmii"))
63 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_GMII_MII;
64 else if (!strcmp(phymode, "rgmii"))
65 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RGMII;
66 else if (!strcmp(phymode, "rmii"))
67 modereg = SYSMGR_EMACGRP_CTRL_PHYSEL_ENUM_RMII;
71 clrsetbits_le32(&sysmgr_regs->emac0 + gmac_index,
72 SYSMGR_EMACGRP_CTRL_PHYSEL_MASK,
78 static int socfpga_set_phymode(void)
80 const void *fdt = gd->fdt_blob;
81 struct fdtdec_phandle_args args;
84 int nodes[3]; /* Max. 3 GMACs */
88 count = fdtdec_find_aliases_for_id(fdt, "ethernet",
89 COMPAT_ALTERA_SOCFPGA_DWMAC,
90 nodes, ARRAY_SIZE(nodes));
91 for (i = 0; i < count; i++) {
96 ret = fdtdec_parse_phandle_with_args(fdt, node, "resets",
99 if (ret || args.args_count != 1) {
100 debug("GMAC%i: Failed to parse DT 'resets'!\n", i);
104 gmac_index = args.args[0] - EMAC0_RESET;
106 phy_mode = fdt_getprop(fdt, node, "phy-mode", NULL);
107 ret = socfpga_phymode_setup(gmac_index, phy_mode);
109 debug("GMAC%i: Failed to parse DT 'phy-mode'!\n", i);
117 static int socfpga_set_phymode(void)
124 * Print CPU information
126 #if defined(CONFIG_DISPLAY_CPUINFO)
127 int print_cpuinfo(void)
129 puts("CPU: Intel FPGA SoCFPGA Platform (ARMv8 64bit Cortex-A53)\n");
135 #ifdef CONFIG_ARCH_MISC_INIT
136 int arch_misc_init(void)
138 char qspi_string[13];
140 sprintf(qspi_string, "<0x%08x>", cm_get_qspi_controller_clk_hz());
141 env_set("qspi_clock", qspi_string);
143 socfpga_set_phymode();
148 int arch_early_init_r(void)
150 socfpga_fpga_add(&altera_fpga[0]);
155 void do_bridge_reset(int enable, unsigned int mask)
157 /* Check FPGA status before bridge enable */
159 int ret = mbox_get_fpga_config_status(MBOX_RECONFIG_STATUS);
161 if (ret && ret != MBOX_CFGSTAT_STATE_CONFIG)
162 ret = mbox_get_fpga_config_status(MBOX_CONFIG_STATUS);
168 socfpga_bridges_reset(enable);